Re: [PATCH v2 3/6] irqchip/gic-v4.1: Ensure L2 vPE table is allocated at RD level

2020-02-13 Thread Zenghui Yu
Hi Marc, On 2020/2/13 22:22, Marc Zyngier wrote: Hi Zenghui, On 2020-02-06 07:57, Zenghui Yu wrote: In GICv4, we will ensure that level2 vPE table memory is allocated for the specified vpe_id on all v4 ITS, in its_alloc_vpe_table(). This still works well for the typical GICv4.1

Re: [PATCH v2 3/6] irqchip/gic-v4.1: Ensure L2 vPE table is allocated at RD level

2020-02-13 Thread Marc Zyngier
Hi Zenghui, On 2020-02-06 07:57, Zenghui Yu wrote: In GICv4, we will ensure that level2 vPE table memory is allocated for the specified vpe_id on all v4 ITS, in its_alloc_vpe_table(). This still works well for the typical GICv4.1 implementation, where the new vPE table is shared between the

[PATCH v2 3/6] irqchip/gic-v4.1: Ensure L2 vPE table is allocated at RD level

2020-02-05 Thread Zenghui Yu
In GICv4, we will ensure that level2 vPE table memory is allocated for the specified vpe_id on all v4 ITS, in its_alloc_vpe_table(). This still works well for the typical GICv4.1 implementation, where the new vPE table is shared between the ITSs and the RDs. To make it explicit, let us introduce