On 08/09/17 17:05, Christoffer Dall wrote:
> On Fri, Sep 8, 2017 at 4:27 PM, Auger Eric wrote:
>> Hi Marc,
>>
>> On 08/09/2017 15:32, Marc Zyngier wrote:
>>> On 08/09/17 14:04, Auger Eric wrote:
Hi Christoffer,
On 06/09/2017 14:26, Christoffer Dall wrote:
On Fri, Sep 8, 2017 at 4:27 PM, Auger Eric wrote:
> Hi Marc,
>
> On 08/09/2017 15:32, Marc Zyngier wrote:
>> On 08/09/17 14:04, Auger Eric wrote:
>>> Hi Christoffer,
>>>
>>> On 06/09/2017 14:26, Christoffer Dall wrote:
For mapped IRQs (with the HW bit set in the LR) we
Hi Marc,
On 08/09/2017 15:32, Marc Zyngier wrote:
> On 08/09/17 14:04, Auger Eric wrote:
>> Hi Christoffer,
>>
>> On 06/09/2017 14:26, Christoffer Dall wrote:
>>> For mapped IRQs (with the HW bit set in the LR) we have to follow some
>>> rules of the architecture. One of these rules is that VM
On 08/09/17 14:04, Auger Eric wrote:
> Hi Christoffer,
>
> On 06/09/2017 14:26, Christoffer Dall wrote:
>> For mapped IRQs (with the HW bit set in the LR) we have to follow some
>> rules of the architecture. One of these rules is that VM must not be
>> allowed to deactivate a virtual interrupt
Hi Christoffer,
On 06/09/2017 14:26, Christoffer Dall wrote:
> For mapped IRQs (with the HW bit set in the LR) we have to follow some
> rules of the architecture. One of these rules is that VM must not be
> allowed to deactivate a virtual interrupt with the HW bit set unless the
> physical