On Wed, May 6, 2015 at 4:12 PM, Christoffer Dall
christoffer.d...@linaro.org wrote:
Hi Jérémy,
On Tue, May 05, 2015 at 11:13:11AM +0200, Jérémy Fanguède wrote:
To maintain cache coherency on ARM, we may need a mechanism to flush
the data cache.
In addition to generally just making this
On Thu, May 7, 2015 at 1:20 PM, Christoffer Dall
christoffer.d...@linaro.org wrote:
On Thu, May 07, 2015 at 12:50:50PM +0200, Jérémy Fanguède wrote:
On Wed, May 6, 2015 at 4:12 PM, Christoffer Dall
christoffer.d...@linaro.org wrote:
Hi Jérémy,
On Tue, May 05, 2015 at 11:13:11AM +0200,
On Thu, May 7, 2015 at 4:50 PM, Jérémy Fanguède
j.fangu...@virtualopensystems.com wrote:
On Thu, May 7, 2015 at 1:20 PM, Christoffer Dall
christoffer.d...@linaro.org wrote:
On Thu, May 07, 2015 at 12:50:50PM +0200, Jérémy Fanguède wrote:
On Wed, May 6, 2015 at 4:12 PM, Christoffer Dall
On Thu, May 7, 2015 at 5:34 PM, Christoffer Dall
christoffer.d...@linaro.org wrote:
On Thu, May 7, 2015 at 4:50 PM, Jérémy Fanguède
j.fangu...@virtualopensystems.com wrote:
On Thu, May 7, 2015 at 1:20 PM, Christoffer Dall
christoffer.d...@linaro.org wrote:
On Thu, May 07, 2015 at 12:50:50PM
On Thu, May 07, 2015 at 12:50:50PM +0200, Jérémy Fanguède wrote:
On Wed, May 6, 2015 at 4:12 PM, Christoffer Dall
christoffer.d...@linaro.org wrote:
Hi Jérémy,
On Tue, May 05, 2015 at 11:13:11AM +0200, Jérémy Fanguède wrote:
To maintain cache coherency on ARM, we may need a mechanism to
Hi Jérémy,
On Tue, May 05, 2015 at 11:13:11AM +0200, Jérémy Fanguède wrote:
To maintain cache coherency on ARM, we may need a mechanism to flush
the data cache.
In addition to generally just making this functionality available (see
below), do you have an actual use case in mind for this? To
To maintain cache coherency on ARM, we may need a mechanism to flush
the data cache.
This patch implements KVM_FLUSH_DCACHE_GPA vm ioctl which flushes the
data cache at a specified address range. The input argument is a
struct kvm_mem_addr containing the guest physical address and the
length.
