Hi Marc , Peter
On Sat, Sep 17, 2016 at 5:07 PM, Marc Zyngier wrote:
> On Sat, 17 Sep 2016 11:58:48 +0530
> Vijay Kilari wrote:
>
>> On Fri, Sep 16, 2016 at 10:37 PM, Marc Zyngier wrote:
>> > On 16/09/16 17:57, Vijay Kilari wrote:
>> >> On Fri, Sep 16, 2016 at 8:06 PM, Marc Zyngier
>> >> wrot
On Fri, Sep 16, 2016 at 09:36:42PM +0200, Alexander Graf wrote:
>
>
> > Am 16.09.2016 um 15:46 schrieb Andrew Jones :
> >
> >> On Fri, Sep 16, 2016 at 03:30:27PM +0200, Christoffer Dall wrote:
> >>> On Fri, Sep 16, 2016 at 02:31:42PM +0200, Paolo Bonzini wrote:
> >>>
> >>>
> >>> On 16/09/2016
On 19 September 2016 at 08:36, Vijay Kilari wrote:
> In order to track the PRI and ID bits written by guest,
> VGIC needs to store these values when ICC_CTRL_EL1 is updated.
> However, QEMU is reseting VGIC by writing 0's to all the
> registers after VGIC initialization and hence the back up valu
On 16.09.16 15:30, Christoffer Dall wrote:
> On Fri, Sep 16, 2016 at 02:31:42PM +0200, Paolo Bonzini wrote:
>>
>>
>> On 16/09/2016 14:30, Christoffer Dall wrote:
>> This patch set allows user space to receive vtimer events as well as mask
>> them, so that we can handle all vtimer related
We have 2 modes for dealing with interrupts in the ARM world. We can either
handle them all using hardware acceleration through the vgic or we can emulate
a gic in user space and only drive CPU IRQ pins from there.
Unfortunately, when driving IRQs from user space, we never tell user space
about ti
Some systems out there (well, one type in particular - the Raspberry Pi series)
do have virtualization capabilities in the core, but no ARM GIC interrupt
controller.
To run on these systems, the cleanest route is to just handle all
interrupt delivery in user space and only deal with IRQ pins in th
In a follow-up patch we will need to enable capabilities on demand for
backwards compatibility. This patch adds the generic framework to handle
vcpu cap enablement to the arm code base.
Signed-off-by: Alexander Graf
---
Documentation/virtual/kvm/api.txt | 4 +++-
arch/arm/kvm/arm.c
On Mon, Sep 19, 2016 at 12:51:46PM +0200, Alexander Graf wrote:
>
>
> On 16.09.16 15:30, Christoffer Dall wrote:
[...]
> >
> > That being said, I'm not categorically against these patches, but I
> > share Marc's view that we've already seen that non-vgic support had been
> > broken for multipl
All virtualization capable ARM cores support the ARM architected virtual timer.
This patch adds minimalistic checks whether we can fire a virtual timer event
using them. It does not actually trigger an interrupt yet, as infrastructure
for that is missing. However, it does check whether the timer p
On 19.09.16 09:52, Andrew Jones wrote:
> On Fri, Sep 16, 2016 at 09:36:42PM +0200, Alexander Graf wrote:
>>
>>
>>> Am 16.09.2016 um 15:46 schrieb Andrew Jones :
>>>
On Fri, Sep 16, 2016 at 03:30:27PM +0200, Christoffer Dall wrote:
> On Fri, Sep 16, 2016 at 02:31:42PM +0200, Paolo Bonzini
On 19/09/16 12:14, Alexander Graf wrote:
> We have 2 modes for dealing with interrupts in the ARM world. We can either
> handle them all using hardware acceleration through the vgic or we can emulate
> a gic in user space and only drive CPU IRQ pins from there.
>
> Unfortunately, when driving IRQs
On Mon, Sep 19, 2016 at 01:44:40PM +0200, Alexander Graf wrote:
> All virtualization capable ARM cores support the ARM architected virtual
> timer.
>
> This patch adds minimalistic checks whether we can fire a virtual timer event
> using them. It does not actually trigger an interrupt yet, as inf
On 19.09.16 16:48, Marc Zyngier wrote:
> On 19/09/16 12:14, Alexander Graf wrote:
>> We have 2 modes for dealing with interrupts in the ARM world. We can either
>> handle them all using hardware acceleration through the vgic or we can
>> emulate
>> a gic in user space and only drive CPU IRQ pins
From: Vijaya Kumar K
ICC_VMCR_EL2 supports virtual access to ICC_IGRPEN1_EL1.Enable
and ICC_IGRPEN0_EL1.Enable fields. Add grpen0 and grpen1 member
variables to struct vmcr to support read and write of these fields.
Also refactor vgic_set_vmcr and vgic_get_vmcr() code.
Drop ICH_VMCR_CTLR_SHIFT a
From: Vijaya Kumar K
In order to implement vGICv3 CPU interface access, we will need to perform
table lookup of system registers. We would need both index_to_params() and
find_reg() exported for that purpose, but instead we export a single
function which combines them both.
Signed-off-by: Pavel
From: Vijaya Kumar K
Userspace requires to store and restore of line_level for
level triggered interrupts using ioctl KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO.
Signed-off-by: Vijaya Kumar K
---
arch/arm64/include/uapi/asm/kvm.h | 6 +
virt/kvm/arm/vgic/vgic-kvm-device.c | 50
From: Vijaya Kumar K
This patchset adds API for saving and restoring
of VGICv3 registers to support live migration with new vgic feature.
This API definition is as per version of VGICv3 specification
http://lists.infradead.org/pipermail/linux-arm-kernel/2016-July/445611.html
Compatible live migr
From: Vijaya Kumar K
Define register definitions for ICH_VMCR_EL2, ICC_CTLR_EL1 and
ICH_VTR_EL2, ICC_BPR0_EL1, ICC_BPR1_EL1 registers.
Signed-off-by: Vijaya Kumar K
---
include/linux/irqchip/arm-gic-v3.h | 43 --
1 file changed, 41 insertions(+), 2 deletions
From: Vijaya Kumar K
Read and write of some registers like ISPENDR and ICPENDR
from userspace requires special handling when compared to
guest access for these registers.
Refer to Documentation/virtual/kvm/devices/arm-vgic-v3.txt
for handling of ISPENDR, ICPENDR registers handling.
Add infrastr
From: Vijaya Kumar K
VGICv3 CPU interface registers are accessed using
KVM_DEV_ARM_VGIC_CPU_SYSREGS ioctl. These registers are accessed
as 64-bit. The cpu MPIDR value is passed along with register id.
is used to identify the cpu for registers access.
The version of VGIC v3 specification is defin
From: Vijaya Kumar K
VGICv3 Distributor and Redistributor registers are accessed using
KVM_DEV_ARM_VGIC_GRP_DIST_REGS and KVM_DEV_ARM_VGIC_GRP_DIST_REGS
with KVM_SET_DEVICE_ATTR and KVM_GET_DEVICE_ATTR ioctls.
These registers are accessed as 32-bit and cpu mpidr
value passed along with register o
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