Hi Tyler,
On 20/01/17 20:58, Baicar, Tyler wrote:
> On 1/19/2017 10:57 AM, James Morse wrote:
>> On 18/01/17 23:51, Baicar, Tyler wrote:
>>> On 1/18/2017 7:50 AM, James Morse wrote:
On 12/01/17 18:15, Tyler Baicar wrote:
> diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c
On 24/01/17 05:06, Linu Cherian wrote:
> On Sat, Jan 14, 2017 at 9:53 PM, Geetha Akula
> wrote:
>> Hi Marc,
>>
>> We have been testing vfio patches regularly. We are in contact with Eric
>> offline. In fact we are the first one to test V5 patches on Eric request as
On 1/24/2017 10:55 AM, James Morse wrote:
Hi Tyler,
On 20/01/17 20:58, Baicar, Tyler wrote:
On 1/19/2017 10:57 AM, James Morse wrote:
On 18/01/17 23:51, Baicar, Tyler wrote:
On 1/18/2017 7:50 AM, James Morse wrote:
On 12/01/17 18:15, Tyler Baicar wrote:
diff --git
On 1/23/2017 3:01 AM, James Morse wrote:
Hi Tyler,
On 20/01/17 20:35, Baicar, Tyler wrote:
On 1/19/2017 10:55 AM, James Morse wrote:
On 18/01/17 23:26, Baicar, Tyler wrote:
On 1/17/2017 3:31 AM, James Morse wrote:
On 12/01/17 18:15, Tyler Baicar wrote:
+info.si_addr = (void __user
On 23/01/17 21:08, Christoffer Dall wrote:
> On Fri, Jan 20, 2017 at 10:50:10AM +, Sudeep Holla wrote:
>> csselr and ccsidr are treated as 64-bit values already elsewhere in the
>> kernel. It also aligns well with the architecture extensions that allow
>> 64-bit format for ccsidr.
>>
>> This
Hi,
so I gave this patch (adapted to live without the soft_pending state)
some testing on my machines (Midway, Juno, GICv3 ITS h/w) and it seemed
to work well - at least if one is nice and starts only one process
accessing vgic-state (see below). I caught some IRQs red-handed and the
output
On 24/01/17 10:30, Christoffer Dall wrote:
> On Tue, Jan 24, 2017 at 10:15:38AM +, Sudeep Holla wrote:
>>
>>
>> On 23/01/17 21:08, Christoffer Dall wrote:
>>> On Fri, Jan 20, 2017 at 10:50:10AM +, Sudeep Holla wrote:
csselr and ccsidr are treated as 64-bit values already elsewhere
Hi Christoffer,
On 23/01/17 18:34, Christoffer Dall wrote:
> On Mon, Jan 23, 2017 at 05:57:05PM +, Andre Przywara wrote:
>> Hi Christoffer,
>>
>> On 23/01/17 13:39, Christoffer Dall wrote:
>>> One of the goals behind the VGIC redesign was to get rid of cached or
>>> intermediate state in the
On Tue, Jan 24, 2017 at 10:15:38AM +, Sudeep Holla wrote:
>
>
> On 23/01/17 21:08, Christoffer Dall wrote:
> > On Fri, Jan 20, 2017 at 10:50:10AM +, Sudeep Holla wrote:
> >> csselr and ccsidr are treated as 64-bit values already elsewhere in the
> >> kernel. It also aligns well with the
On Tue, Jan 24, 2017 at 10:23:57AM +, Andre Przywara wrote:
> Hi,
>
> so I gave this patch (adapted to live without the soft_pending state)
> some testing on my machines (Midway, Juno, GICv3 ITS h/w) and it seemed
> to work well - at least if one is nice and starts only one process
>
On 23/01/17 21:05, Christoffer Dall wrote:
> On Fri, Jan 20, 2017 at 10:50:09AM +, Sudeep Holla wrote:
>> We already have various macros related to cache type and bitfields in
>> CLIDR system register. We can replace some of the hardcoded values
>> here using those existing macros.
>>
>>
On Tue, Jan 24, 2017 at 10:01:07AM +, Andre Przywara wrote:
> Hi Christoffer,
>
> On 23/01/17 18:34, Christoffer Dall wrote:
> > On Mon, Jan 23, 2017 at 05:57:05PM +, Andre Przywara wrote:
> >> Hi Christoffer,
> >>
> >> On 23/01/17 13:39, Christoffer Dall wrote:
> >>> One of the goals
One of the goals behind the VGIC redesign was to get rid of cached or
intermediate state in the data structures, but we decided to allow
ourselves to precompute the pending value of an IRQ based on the line
level and pending latch state. However, this has now become difficult
to base proper GICv3
On Tue, Jan 24, 2017 at 10:55:24AM +, Sudeep Holla wrote:
>
>
> On 24/01/17 10:30, Christoffer Dall wrote:
> > On Tue, Jan 24, 2017 at 10:15:38AM +, Sudeep Holla wrote:
> >>
> >>
> >> On 23/01/17 21:08, Christoffer Dall wrote:
> >>> On Fri, Jan 20, 2017 at 10:50:10AM +, Sudeep Holla
Hi,
[...]
As I didn't understand the seq_* semantics in the first place, I didn't
have a look yet what could cause this.
>>>
>>> Nice catch, I'll have a look at this.
>>>
>>> Just so I'm sure, these are two processes reading the vgic-state file
>>> for the same single VM, right?
On Tue, Jan 24, 2017 at 12:25:25PM +, Andre Przywara wrote:
> Hi,
>
> On 24/01/17 10:58, Christoffer Dall wrote:
> > On Tue, Jan 24, 2017 at 10:23:57AM +, Andre Przywara wrote:
> >> Hi,
> >>
> >> so I gave this patch (adapted to live without the soft_pending state)
> >> some testing on my
Hi,
On 24/01/17 10:58, Christoffer Dall wrote:
> On Tue, Jan 24, 2017 at 10:23:57AM +, Andre Przywara wrote:
>> Hi,
>>
>> so I gave this patch (adapted to live without the soft_pending state)
>> some testing on my machines (Midway, Juno, GICv3 ITS h/w) and it seemed
>> to work well - at least
Hi Will,
On 01/13/2017 11:12 AM, Will Deacon wrote:
> On Fri, Jan 13, 2017 at 10:12:36AM -0500, Christopher Covington wrote:
>> On 01/12/2017 11:58 AM, Will Deacon wrote:
>>> On Wed, Jan 11, 2017 at 09:41:16AM -0500, Christopher Covington wrote:
+#define __tlbi_asm_dsb(as, op, attr, ...) do
Hi Christoffer,
[auto build test ERROR on kvmarm/next]
[also build test ERROR on v4.10-rc5 next-20170124]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Christoffer-Dall/KVM-arm-arm64-vgic-Add
Hi Catalin,
On 01/11/2017 01:06 PM, Catalin Marinas wrote:
> Some minor comments below, nothing fundamental (as long as you say the
> new sequence doesn't have the speculative TLB load problem I mentioned
> on a previous version).
This workaround is documented as providing functional correctness
Add a file to debugfs to read the in-kernel state of the vgic. We don't
do any locking of the entire VGIC state while traversing all the IRQs,
so if the VM is running the user/developer may not see a quiesced state,
but should take care to pause the VM using facilities in user space for
that
On 01/12/2017 11:12 AM, Mark Rutland wrote:
> On Thu, Jan 12, 2017 at 03:45:48PM +, Catalin Marinas wrote:
>> On Wed, Jan 11, 2017 at 06:40:52PM +, Mark Rutland wrote:
>
>>> Likewise, I beleive we may need to modify cpu_set_reserved_ttbr0().
>>
>> This may be fine if my assumptions about
On Tue, Jan 24, 2017 at 10:23:57AM +, Andre Przywara wrote:
> Hi,
>
> so I gave this patch (adapted to live without the soft_pending state)
> some testing on my machines (Midway, Juno, GICv3 ITS h/w) and it seemed
> to work well - at least if one is nice and starts only one process
>
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