Re: [PATCH v4 2/4] arm64: Work around Falkor erratum 1003

On 01/25/2017 09:52 AM, Christopher Covington wrote: + .desc = "Qualcomm Falkor erratum 1003", FYI, this needs to say, "Qualcomm Technologies Falkor ...". Same thing with the 1009 patch. -- Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc.

Re: [PATCH v11 1/8] arm/arm64: vgic: Implement support for userspace access

Hi, On 26/01/2017 15:20, vijay.kil...@gmail.com wrote: > From: Vijaya Kumar K > > Read and write of some registers like ISPENDR and ICPENDR > from userspace requires special handling when compared to > guest access for these registers. > > Refer to

Re: [PATCH v11 2/8] arm/arm64: vgic: Add distributor and redistributor access

Hi, On 26/01/2017 15:20, vijay.kil...@gmail.com wrote: > From: Vijaya Kumar K > > VGICv3 Distributor and Redistributor registers are accessed using > KVM_DEV_ARM_VGIC_GRP_DIST_REGS and KVM_DEV_ARM_VGIC_GRP_REDIST_REGS > with KVM_SET_DEVICE_ATTR and KVM_GET_DEVICE_ATTR

Re: [PATCH v11 5/8] arm/arm64: vgic: Introduce VENG0 and VENG1 fields to vmcr struct

Hi, On 26/01/2017 15:20, vijay.kil...@gmail.com wrote: > From: Vijaya Kumar K > > ICC_VMCR_EL2 supports virtual access to ICC_IGRPEN1_EL1.Enable > and ICC_IGRPEN0_EL1.Enable fields. Add grpen0 and grpen1 member > variables to struct vmcr to support read and write of

Re: [PATCH v11 6/8] arm/arm64: vgic: Implement VGICv3 CPU interface access

Hi, On 26/01/2017 15:20, vijay.kil...@gmail.com wrote: > From: Vijaya Kumar K > > VGICv3 CPU interface registers are accessed using > KVM_DEV_ARM_VGIC_CPU_SYSREGS ioctl. These registers are accessed > as 64-bit. The cpu MPIDR value is passed along with register id. > It

Re: [PATCH v11 7/8] arm/arm64: vgic: Implement KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO ioctl

Hi, On 26/01/2017 15:20, vijay.kil...@gmail.com wrote: > From: Vijaya Kumar K > > Userspace requires to store and restore of line_level for > level triggered interrupts using ioctl KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO. > > Signed-off-by: Vijaya Kumar K

Re: [PATCH v11 7/8] arm/arm64: vgic: Implement KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO ioctl

Hi, On 27/01/2017 09:32, Auger Eric wrote: > Hi, > > On 26/01/2017 15:20, vijay.kil...@gmail.com wrote: >> From: Vijaya Kumar K >> >> Userspace requires to store and restore of line_level for >> level triggered interrupts using ioctl KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO. >>

Re: [PATCH v11 8/8] arm/arm64: Documentation: Update arm-vgic-v3.txt

Hi Vijaya, On 26/01/2017 15:20, vijay.kil...@gmail.com wrote: > From: Vijaya Kumar K > > Update error code returned for Invalid CPU interface register > value and access in AArch32 mode. > > Signed-off-by: Vijaya Kumar K Reviewed-by: Eric

Re: [PATCH v11 0/8] arm/arm64: vgic: Implement API for vGICv3 live migration

Hi Vijaya, On 26/01/2017 15:20, vijay.kil...@gmail.com wrote: > From: Vijaya Kumar K > > This patchset adds API for saving and restoring > of VGICv3 registers to support live migration with new vgic feature. > This API definition is as per version of VGICv3

Re: [PATCH v11 0/8] arm/arm64: vgic: Implement API for vGICv3 live migration

On 26/01/17 20:26, Christoffer Dall wrote: > Hi Vijaya, > > On Thu, Jan 26, 2017 at 07:50:45PM +0530, vijay.kil...@gmail.com wrote: >> From: Vijaya Kumar K >> >> This patchset adds API for saving and restoring >> of VGICv3 registers to support live migration with new

Re: [PATCH v11 0/8] arm/arm64: vgic: Implement API for vGICv3 live migration

On Fri, Jan 27, 2017 at 09:45:06AM +, Marc Zyngier wrote: > On 26/01/17 20:26, Christoffer Dall wrote: > > Hi Vijaya, > > > > On Thu, Jan 26, 2017 at 07:50:45PM +0530, vijay.kil...@gmail.com wrote: > >> From: Vijaya Kumar K > >> > >> This patchset adds API for saving

Re: [PATCH v4 3/4] arm64: Use __tlbi() macros in KVM code

On Wed, Jan 25, 2017 at 08:39:43PM +0100, Christoffer Dall wrote: > On Wed, Jan 25, 2017 at 10:52:31AM -0500, Christopher Covington wrote: > > Refactor the KVM code to use the __tlbi macros, which will allow an errata > > workaround that repeats tlbi dsb sequences to only change one location. > >

Re: [PATCH v4 2/4] arm64: Work around Falkor erratum 1003

On Wed, Jan 25, 2017 at 10:52:30AM -0500, Christopher Covington wrote: > The Qualcomm Datacenter Technologies Falkor v1 CPU may allocate TLB entries > using an incorrect ASID when TTBRx_EL1 is being updated. When the erratum > is triggered, page table entries using the new translation table base >

Re: [PATCH] KVM: arm64: Increase number of memslots to 512

> Can you shed some light on your test process? Hi Linu / Marc Zyngier, I tested this patch on top of latest VFIO MSI supported version 9 patches on ThunderX with internal 10G VNIC and Intel IXGBE NIC. Please feel free to add my: Tested-by: Prakash, Brahmajyosyula

Re: [PATCH v4 2/4] arm64: Work around Falkor erratum 1003

On Fri, Jan 27, 2017 at 02:38:49PM +, Mark Rutland wrote: > IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended > recipient, please notify the sender immediately and do not disclose > the contents to any

Re: [PATCH v4 3/4] arm64: Use __tlbi() macros in KVM code

On Wed, Jan 25, 2017 at 10:52:31AM -0500, Christopher Covington wrote: > Refactor the KVM code to use the __tlbi macros, which will allow an errata > workaround that repeats tlbi dsb sequences to only change one location. > This is not intended to change the generated assembly and comparing before

Re: [PATCH v4 4/4] arm64: Work around Falkor erratum 1009

On Wed, Jan 25, 2017 at 10:52:32AM -0500, Christopher Covington wrote: > During a TLB invalidate sequence targeting the inner shareable domain, > Falkor may prematurely complete the DSB before all loads and stores using > the old translation are observed. Instruction fetches are not subject to >

Re: [PATCH v4 2/4] arm64: Work around Falkor erratum 1003

Hi Mark, On 01/27/2017 09:38 AM, Mark Rutland wrote: > On Wed, Jan 25, 2017 at 10:52:30AM -0500, Christopher Covington wrote: >> The Qualcomm Datacenter Technologies Falkor v1 CPU may allocate TLB entries >> using an incorrect ASID when TTBRx_EL1 is being updated. When the erratum >> is