[PATCH v2 2/2] arm64: Add software workaround for Falkor erratum 1041

2017-11-12 Thread Shanker Donthineni
The ARM architecture defines the memory locations that are permitted to be accessed as the result of a speculative instruction fetch from an exception level for which all stages of translation are disabled. Specifically, the core is permitted to speculatively fetch from the 4KB region containing

[PATCH v2 1/2] arm64: Define cputype macros for Falkor CPU

2017-11-12 Thread Shanker Donthineni
Add cputype definition macros for Qualcomm Datacenter Technologies Falkor CPU in cputype.h. It's unfortunate that the first revision of the Falkor CPU used the wrong part number 0x800, got fixed in v2 chip with part number 0xC00, and would be used the same value for future revisions.

[PATCH v2 0/2] Implement a software workaround for Falkor erratum 1041

2017-11-12 Thread Shanker Donthineni
On Falkor CPU, we’ve discovered a hardware issue which might lead to a kernel crash or the unexpected behavior. The Falkor core may errantly access memory locations on speculative instruction fetches. This may happen whenever MMU translation state, SCTLR_ELn[M] bit is being changed from enabled to

[PATCH v3 0/2] Implement a software workaround for Falkor erratum 1041

2017-11-12 Thread Shanker Donthineni
On Falkor CPU, we’ve discovered a hardware issue which might lead to a kernel crash or the unexpected behavior. The Falkor core may errantly access memory locations on speculative instruction fetches. This may happen whenever MMU translation state, SCTLR_ELn[M] bit is being changed from enabled to

[PATCH v3 1/2] arm64: Define cputype macros for Falkor CPU

2017-11-12 Thread Shanker Donthineni
Add cputype definition macros for Qualcomm Datacenter Technologies Falkor CPU in cputype.h. It's unfortunate that the first revision of the Falkor CPU used the wrong part number 0x800, got fixed in v2 chip with part number 0xC00, and would be used the same value for future revisions.

[PATCH v3 2/2] arm64: Add software workaround for Falkor erratum 1041

2017-11-12 Thread Shanker Donthineni
The ARM architecture defines the memory locations that are permitted to be accessed as the result of a speculative instruction fetch from an exception level for which all stages of translation are disabled. Specifically, the core is permitted to speculatively fetch from the 4KB region containing

Re: [PATCH 3/3] arm64: Add software workaround for Falkor erratum 1041

2017-11-12 Thread Shanker Donthineni
Hi James, On 11/10/2017 04:24 AM, James Morse wrote: > Hi Shanker, > > On 09/11/17 15:22, Shanker Donthineni wrote: >> On 11/09/2017 05:08 AM, James Morse wrote: >>> On 04/11/17 21:43, Shanker Donthineni wrote: On 11/03/2017 10:11 AM, Robin Murphy wrote: > On 03/11/17 03:27, Shanker

Re: [PATCH v2 2/2] arm64: Add software workaround for Falkor erratum 1041

2017-11-12 Thread Shanker Donthineni
Hi, Sorry, I've posted a wrong patch which causes the compilation errors. Please disregard this patch, I posted v3 patch to fix the build issue. https://patchwork.kernel.org/patch/10055077/ On 11/12/2017 07:16 PM, Shanker Donthineni wrote: > The ARM architecture defines the memory locations