Re: [RFC PATCH] KVM: arm/arm64: vgic: change condition for level interrupt resampling

Hi, Marc, On Sun, 2018-03-11 at 12:17 +, Marc Zyngier wrote: > On Sun, 11 Mar 2018 01:55:08 + > Christoffer Dall wrote: > > > > > On Sat, Mar 10, 2018 at 12:20 PM, Marc Zyngier > m> wrote: > > > > > > On Fri, 09 Mar 2018 21:36:12 +, > > >

[PATCH v2 2/2] kvm: arm/arm64: vgic-v3: Tighten synchronization for guests using v2 on v3

On guest exit, and when using GICv2 on GICv3, we use a dsb(st) to force synchronization between the memory-mapped guest view and the system-register view that the hypervisor uses. This is incorrect, as the spec calls out the need for "a DSB whose required access type is both loads and stores with

[PATCH v2 1/2] KVM: arm/arm64: vgic: Don't populate multiple LRs with the same vintid

The vgic code is trying to be clever when injecting GICv2 SGIs, and will happily populate LRs with the same interrupt number if they come from multiple vcpus (after all, they are distinct interrupt sources). Unfortunately, this is against the letter of the architecture, and the GICv2 architecture