On Thu, Feb 19, 2015 at 06:57:24PM +0100, Paolo Bonzini wrote:
On 19/02/2015 18:55, Andrew Jones wrote:
(I don't have an exact number for how many times it went to EL1 because
access_mair() doesn't have a trace point.)
(I got the 62873 number by testing a 3rd kernel build
On Thu, Feb 19, 2015 at 10:54:43AM +, Ard Biesheuvel wrote:
This is a 0th order approximation of how we could potentially force the guest
to avoid uncached mappings, at least from the moment the MMU is on. (Before
that, all of memory is implicitly classified as Device-nGnRnE)
The idea
On Thu, Mar 19, 2015 at 05:56:20PM +0100, Paolo Bonzini wrote:
On 18/03/2015 20:10, Andrew Jones wrote:
Introduce a new memory region flag, KVM_MEM_UNCACHED, which
is needed by ARM. This flag informs KVM that the given memory
region is typically mapped by the guest as uncached. KVM
Should do a proper update-linux-headers.sh update.
Signed-off-by: Andrew Jones drjo...@redhat.com
---
linux-headers/linux/kvm.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
index 60a54c82a3b76..34c03cd80aa69 100644
--- a/linux
In reply to this message I'll send two series' one for KVM and
one for QEMU. The two series' are their respective component
complements, and attempt to implement cache coherency for arm
guests using emulated devices, where the emulator (qemu) uses
cached memory for the device memory, but the guest
Also rename to KVM_MEM_UNCACHED.
Signed-off-by: Andrew Jones drjo...@redhat.com
---
Documentation/virtual/kvm/api.txt | 16 ++--
arch/arm/include/uapi/asm/kvm.h | 1 +
arch/arm/kvm/arm.c| 1 +
arch/arm/kvm/mmu.c| 4 ++--
arch/arm64/include/uapi
Currently kvm_mem_flags just translates bools to bits, let's
make it also determine the bools first. This avoids its parameter
list growing each time we add a flag.
Signed-off-by: Andrew Jones drjo...@redhat.com
---
kvm-all.c | 25 +++--
1 file changed, 15 insertions(+), 10
Add support for the new KVM_MEM_UNCACHED flag, and flag
appropriate memory. (Only flags vga/vram for now.)
Andrew Jones (4):
kvm-all: put kvm_mem_flags to more work
HACK: linux header update
memory: add uncached flag
vga: flag vram as uncached
hw/display/vga.c | 1 +
include
On Wed, Mar 18, 2015 at 03:08:20PM -0400, Andrew Jones wrote:
In reply to this message I'll send two series' one for KVM and
one for QEMU. The two series' are their respective component
complements, and attempt to implement cache coherency for arm
guests using emulated devices, where
On Fri, Mar 06, 2015 at 01:08:29PM -0800, Mario Smarduch wrote:
On 03/05/2015 09:43 AM, Paolo Bonzini wrote:
On 05/03/2015 15:58, Catalin Marinas wrote:
It would especially suck if the user has a cluster with different
machines, some of them coherent and others non-coherent, and then
On Wed, Mar 11, 2015 at 02:20:56PM +0100, Christoffer Dall wrote:
On Wed, Mar 11, 2015 at 2:13 PM, Marc Zyngier marc.zyng...@arm.com wrote:
Hi Christoffer,
On 11/03/15 12:16, Christoffer Dall wrote:
Hi Marc,
On Tue, Mar 10, 2015 at 07:06:59PM +, Marc Zyngier wrote:
We're using
Add two new memslot functions to the API
kvm_flush_incoherent_memory_regions
flush all KVM_MEM_INCOHERENT memslot addresses
kvm_invalidate_incoherent_memory_regions
invalidate all KVM_MEM_INCOHERENT memslot addresses
Signed-off-by: Andrew Jones drjo...@redhat.com
---
include/linux
Signed-off-by: Andrew Jones drjo...@redhat.com
---
kvm-all.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/kvm-all.c b/kvm-all.c
index 507fa7204e062..924b4a0bec21c 100644
--- a/kvm-all.c
+++ b/kvm-all.c
@@ -305,6 +305,9 @@ static int kvm_mem_flags(MemoryRegion *mr)
if (readonly
In reply to this message I'll send two series' one for KVM and
one for QEMU. The two series' are their respective component
complements, and attempt to implement cache coherency for arm
guests using emulated devices, where the emulator (qemu) uses
cached memory for the device memory, but the guest
Userspace flags memory regions as incoherent and kvm flushes/
invalidates those regions on entry/exit from userspace.
Result before patch 6/6: restores coherency, way t sloow
Result with patch 6/6: fast again - well, we removed the code...
Andrew Jones (6):
kvm: promote
Add the kvm_*_incoherent_memory_regions calls to arm's
kvm_arch_vcpu_ioctl_run and implement the corresponding
arch flush/invalidate functions.
Signed-off-by: Andrew Jones drjo...@redhat.com
---
arch/arm/include/uapi/asm/kvm.h | 1 +
arch/arm/kvm/arm.c| 4 +++
arch/arm/kvm
Should do a proper update-linux-headers.sh update.
Signed-off-by: Andrew Jones drjo...@redhat.com
---
linux-headers/linux/kvm.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
index 12045a11c036b..d04e2d781c43b 100644
--- a/linux-headers
On Fri, Feb 20, 2015 at 02:37:25PM +, Ard Biesheuvel wrote:
On 20 February 2015 at 14:29, Andrew Jones drjo...@redhat.com wrote:
So looks like the 3 orders of magnitude greater number of traps
(only to el2) don't impact kernel compiles.
OK, good! That was what I was hoping
On Tue, Feb 24, 2015 at 05:47:19PM +, Ard Biesheuvel wrote:
On 24 February 2015 at 14:55, Andrew Jones drjo...@redhat.com wrote:
On Fri, Feb 20, 2015 at 04:36:26PM +0100, Andrew Jones wrote:
On Fri, Feb 20, 2015 at 02:37:25PM +, Ard Biesheuvel wrote:
On 20 February 2015 at 14:29
On Wed, Apr 29, 2015 at 10:19:55AM +0100, Peter Maydell wrote:
On 29 April 2015 at 10:03, Alexander Graf ag...@suse.de wrote:
On 18.03.15 20:10, Andrew Jones wrote:
Introduce a new memory region flag, KVM_MEM_UNCACHED, which
is needed by ARM. This flag informs KVM that the given memory
Provide a method to change normal, cacheable memory to non-cacheable.
KVM will make use of this to keep emulated device memory regions
coherent with the guest.
Signed-off-by: Andrew Jones drjo...@redhat.com
---
arch/arm/include/asm/cacheflush.h | 1 +
arch/arm/mm/pageattr.c | 7
On Thu, May 14, 2015 at 11:37:46AM +0100, Peter Maydell wrote:
On 14 May 2015 at 11:31, Andrew Jones drjo...@redhat.com wrote:
Forgot to (4): switch from setting userspace's mapping to
device memory to normal, non-cacheable. Using device memory
caused a problem that Alex Graf found
On Thu, May 14, 2015 at 01:38:11PM +0100, Peter Maydell wrote:
On 14 May 2015 at 13:28, Paolo Bonzini pbonz...@redhat.com wrote:
Well, PCI BARs are generally MMIO resources, and hence should not be cached.
As an optimization, OS drivers can mark them as cacheable or
write-combining or
On Thu, May 14, 2015 at 01:05:09PM +0200, Christoffer Dall wrote:
On Wed, May 13, 2015 at 01:31:52PM +0200, Andrew Jones wrote:
Provide a method to change normal, cacheable memory to non-cacheable.
KVM will make use of this to keep emulated device memory regions
coherent with the guest
On Wed, May 13, 2015 at 01:31:51PM +0200, Andrew Jones wrote:
Introduce a new memory region flag, KVM_MEM_UNCACHED, which is
needed by ARM. This flag informs KVM that the given memory region
is typically mapped by the guest as non-cacheable. KVM for ARM
then ensures that that memory is indeed
Hi Catalin,
Thanks for the feedback. Some comments to your comments below.
On Mon, May 18, 2015 at 04:53:03PM +0100, Catalin Marinas wrote:
On Thu, May 14, 2015 at 02:46:44PM +0100, Andrew Jones wrote:
On Thu, May 14, 2015 at 01:05:09PM +0200, Christoffer Dall wrote:
On Wed, May 13, 2015
On Mon, Apr 13, 2015 at 11:46:36AM +0100, Mark Rutland wrote:
Hi,
Otherwise the is_guest() function would be many if-else statements
trying to determine the type of guest it is before it even knows that
it is a guest.
It's worth noting that to some extent this may always be
On Wed, Apr 01, 2015 at 06:28:55PM +0200, David Hildenbrand wrote:
This is a precursor for later patches which will need to do more to
setup debug state before entering the hyp.S switch code. The existing
functionality for setting mdcr_el2 has been moved out of hyp.S and now
uses the value
On Wed, Apr 01, 2015 at 05:55:29PM +0200, David Hildenbrand wrote:
This commit adds a stub function to support the KVM_SET_GUEST_DEBUG
ioctl. Currently any operation flag will return EINVAL. Actual
Well it won't return -EINVAL if you push in KVM_GUESTDBG_ENABLE or 0.
Any unsupported flag
On Thu, Apr 09, 2015 at 03:00:27PM +0100, Mark Rutland wrote:
While the HVC immediate could be used to distinguish different types of
calls, the guest still needs to first determine that issuing a HVC is
not going to bring down the system, which requires it to know that a
suitable
On Tue, Mar 31, 2015 at 04:08:05PM +0100, Alex Bennée wrote:
This adds support for single-stepping the guest. As userspace can and
will manipulate guest registers before restarting any tweaking of the
registers has to occur just before control is passed back to the guest.
Furthermore while
by Andrew Jones)
* Rewrite arch_timer ACPI PPI parsing code
* Verified patches on APM Mustang machine, which has arch_timer GICv2
V1:
* Initial patchset
Wei Huang (5):
kvm: arm64: Enable ACPI support for virt arch timer
kvm: arm64: Dispatch virt GIC probing to device tree and ACPI
kvm
On Wed, Jun 10, 2015 at 12:16:03AM -0400, Wei Huang wrote:
This patches enables ACPI support for KVM virtual arch timer. It allows
KVM to parse ACPI table for arch timer PPI when DT table is not present.
Signed-off-by: Alexander Spyridaki a.spyrida...@virtualopensystems.com
Signed-off-by:
On Wed, Jun 10, 2015 at 12:16:07AM -0400, Wei Huang wrote:
This patches enables ACPI support for KVM virtual GICv3. KVM parses
ACPI table for virt GIC related information and initializes resources.
Signed-off-by: Wei Huang w...@redhat.com
---
virt/kvm/arm/vgic-v3.c | 40
structure.
Signed-off-by: Alex Bennée alex.ben...@linaro.org
Reviewed-by: David Hildenbrand d...@linux.vnet.ibm.com
Reviewed-by: Andrew Jones drjo...@redhat.com
Acked-by: Christoffer Dall christoffer.d...@linaro.org
I can re-confirm my ack despite the changes in v4, but this really
While porting the test in virtualopensystems' tcg_baremetal_tests
to kvm-unit-tests, I found a couple places to improve the spinlock
implementation. I also added a way to build a single test that
doesn't necessary have an entry in the makefile, which should be handy
for experimental tests.
Andrew
section
is ordered wrt to what we do outside it, before we announce that
we're outside.
Signed-off-by: Andrew Jones drjo...@redhat.com
---
lib/arm/spinlock.c | 8
lib/arm64/spinlock.c | 5 ++---
2 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/lib/arm/spinlock.c b/lib/arm
' to use it, where some-test matches
the name of the source file, i.e. arm/some-test.c
Signed-off-by: Andrew Jones drjo...@redhat.com
---
config/config-arm-common.mak | 6 ++
1 file changed, 6 insertions(+)
diff --git a/config/config-arm-common.mak b/config/config-arm-common.mak
index
the actual check
back.
Signed-off-by: Andrew Jones drjo...@redhat.com
---
lib/arm/asm/mmu-api.h | 4
lib/arm/mmu.c | 3 +++
2 files changed, 7 insertions(+)
diff --git a/lib/arm/asm/mmu-api.h b/lib/arm/asm/mmu-api.h
index 68dc707d67241..1a4d91163c398 100644
--- a/lib/arm/asm/mmu-api.h
On Thu, Jun 25, 2015 at 06:23:48PM +0200, Paolo Bonzini wrote:
On 25/06/2015 18:12, Andrew Jones wrote:
spinlock torture tests made it clear that checking mmu_enabled()
every time we call spin_lock is a bad idea. As most tests will
want the MMU enabled the entire time, then just hard
Allow unit test cpus to disable the MMU. Why not? We want the
test framework to be as flexible as possible. Callers will have
to deal with the cache coherency fallout... Cache flush support
is still forthcoming to the framework though.
Signed-off-by: Andrew Jones drjo...@redhat.com
---
arm
Andrew Jones (3):
arm/arm64: Introduce mmu_disable
arm/arm64: drop mmu_set_enabled
arm/arm64: speed up spinlocks and atomic ops
arm/cstart.S | 9 +
arm/cstart64.S| 8
lib/arm/asm/mmu-api.h | 9 +++--
lib/arm/mmu.c | 32
-by: Andrew Jones drjo...@redhat.com
---
lib/arm/asm/mmu-api.h | 1 -
lib/arm/mmu.c | 21 ++---
lib/arm/smp.c | 1 -
3 files changed, 10 insertions(+), 13 deletions(-)
diff --git a/lib/arm/asm/mmu-api.h b/lib/arm/asm/mmu-api.h
index c46c4b08b14cc..12fdc57918c27 100644
On Thu, May 28, 2015 at 01:34:33AM -0400, Wei Huang wrote:
This patches enables ACPI support for KVM virtual GICv2. KVM parses
ACPI table for virt GIC related information and initializes resources.
Signed-off-by: Alexander Spyridaki a.spyrida...@virtualopensystems.com
Signed-off-by: Wei
On Mon, Jun 29, 2015 at 12:28:32PM +0200, Christoffer Dall wrote:
On Thu, Jun 25, 2015 at 06:12:18PM +0200, Andrew Jones wrote:
spinlock torture tests made it clear that checking mmu_enabled()
every time we call spin_lock is a bad idea.
why a bad idea? Does it break, is it slow?
Just
On Fri, Jul 03, 2015 at 07:39:13PM +0200, Paolo Bonzini wrote:
On 25/06/2015 20:45, Andrew Jones wrote:
The mmu is enabled automatically for all cpus, they must disable it
themselves if they don't want it on. Switch from managing a cpumask
of enabled cpus to one of disabled cpus
On Mon, Oct 19, 2015 at 11:44:30AM -0400, Christopher Covington wrote:
> Hi Drew,
>
> I appreciate your feedback on these patches.
>
> On 10/18/2015 02:28 PM, Andrew Jones wrote:
>
> >> --- a/arm/pmu.c
> >> +++ b/arm/pmu.c
> >> @@ -37,6 +37,18 @@
On Mon, Oct 26, 2015 at 04:58:43PM +0100, Andrew Jones wrote:
> On Mon, Oct 26, 2015 at 11:38:49AM -0400, Christopher Covington wrote:
> > Ensure that reads of the PMCCNTR_EL0 are monotonically increasing,
> > even for the smallest delta of two subsequent reads.
> >
> >
On Mon, Oct 26, 2015 at 11:38:50AM -0400, Christopher Covington wrote:
> Calculate the numbers of cycles per instruction (CPI) implied by ARM
> PMU cycle counter values. The code includes a strict checking facility
> intended for the -icount option in TCG mode but it is not yet enabled
> in the
On Mon, Nov 02, 2015 at 09:58:14AM -0600, Andrew Jones wrote:
> On Fri, Oct 30, 2015 at 03:32:43PM -0400, Christopher Covington wrote:
> > Hi Drew,
> >
> > On 10/30/2015 09:00 AM, Andrew Jones wrote:
> > > On Wed, Oct 28, 2015 at 03:12:55PM -0400, Christopher Cov
On Fri, Oct 30, 2015 at 03:32:43PM -0400, Christopher Covington wrote:
> Hi Drew,
>
> On 10/30/2015 09:00 AM, Andrew Jones wrote:
> > On Wed, Oct 28, 2015 at 03:12:55PM -0400, Christopher Covington wrote:
> >> Calculate the numbers of cycles per instruction (CPI) impli
On Wed, Oct 28, 2015 at 03:12:55PM -0400, Christopher Covington wrote:
> Calculate the numbers of cycles per instruction (CPI) implied by ARM
> PMU cycle counter values. The code includes a strict checking facility
> intended for the -icount option in TCG mode but it is not yet enabled
> in the
on = \
> $(TEST_DIR)/selftest.flat \
> - $(TEST_DIR)/spinlock-test.flat
> + $(TEST_DIR)/spinlock-test.flat \
> + $(TEST_DIR)/pmu.flat
>
> all: test_cases
>
> @@ -70,3 +71,4 @@ test_cases: $(generated_files) $(tests-common) $(tests)
>
>
On Tue, Oct 06, 2015 at 01:49:24PM -0400, Christopher Covington wrote:
> Beginning with a simple sanity check of the control register, add
> a unit test for the ARM Performance Monitors Unit (PMU).
>
> Signed-off-by: Christopher Covington
> ---
> arm/pmu.c |
On Tue, Oct 06, 2015 at 01:49:25PM -0400, Christopher Covington wrote:
> Ensure that reads of the PMCCNTR_EL0 are monotonically increasing,
> even for the smallest delta of two subsequent reads.
>
> Signed-off-by: Christopher Covington
> ---
> arm/pmu.c | 29
On Tue, Oct 06, 2015 at 01:49:26PM -0400, Christopher Covington wrote:
> Check the numbers of cycles per instruction (CPI) implied by ARM PMU
> cycle counter values. Check that in -icount mode these strictly
> match the specified rate.
>
> Signed-off-by: Christopher Covington
On Mon, Jul 06, 2015 at 02:49:56PM +0200, Eric Auger wrote:
On halt, the guest is forced to exit and prevented from being
re-entered. This is synchronous.
Those two operations will be needed for IRQ forwarding setting.
Signed-off-by: Eric Auger eric.au...@linaro.org
---
RFC v1 - v2:
-
On Mon, Jul 06, 2015 at 02:49:55PM +0200, Eric Auger wrote:
The kvm_vcpu_arch pause field is renamed into power_off to prepare
for the introduction of a new pause field.
Signed-off-by: Eric Auger eric.au...@linaro.org
v4 - v5:
- fix compilation issue on arm64 (add power_off field in
printf("Unknown subtest\n");
> + abort();
> }
>
> return report_summary();
> --
> Qualcomm Innovation Center, Inc.
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
On Tue, Dec 08, 2015 at 09:57:21AM +0300, Pavel Fedin wrote:
> Hello!
>
> > I messed up the "load into xzr" test royally in the last attached patch.
> > It was quite wrong.
>
> Yes, because "mov %0, xzr" is not trapped.
>
> > I have now tested
> >
> > asm volatile(
> > "str %3,
On Fri, Nov 27, 2015 at 06:50:04PM +, Marc Zyngier wrote:
> KVM so far relies on code patching, and is likely to use it more
> in the future. The main issue is that our alternative system works
> at the instruction level, while we'd like to have alternatives at
> the function level.
How about
se problem or
something else strange going on with environments.
kvm-unit-tests patch attached
Thanks,
drew
>From 6576833b5e45801f0226316afae7daf0936a0aee Mon Sep 17 00:00:00 2001
From: Andrew Jones <drjo...@redhat.com>
Date: Fri, 4 Dec 2015 23:55:53 +0100
Subject: [kvm-unit-tests PATCH] arm64: add xzr emulator tes
On Mon, Dec 07, 2015 at 12:48:12PM +0300, Pavel Fedin wrote:
> Hello!
>
> > FYI, I tried writing test cases for this issue with kvm-unit-tests. The
> > issue didn't reproduce for me. It's quite possible my test cases are
> > flawed
>
> Indeed they are, a very little thing fell through again...
On Mon, Dec 07, 2015 at 03:58:11PM -0600, Andrew Jones wrote:
> On Mon, Dec 07, 2015 at 12:48:12PM +0300, Pavel Fedin wrote:
> > Hello!
> >
> > > FYI, I tried writing test cases for this issue with kvm-unit-tests. The
> > > issue didn't reproduce for me.
On Mon, Dec 28, 2015 at 07:33:01AM +0900, Itaru Kitayama wrote:
> Does your Mustang boot via UEFI? Mine does. Mainline v4.4-rc6ish
> seems to have an issue with libstub.
FWIW, 4.4.0-0.rc6.git1.1.fc24.aarch64 boots fine for me (with f23 userspace)
My firmware is a pretty old build though
On Thu, Jan 07, 2016 at 02:56:15PM +, Peter Maydell wrote:
> On 7 January 2016 at 14:49, Shannon Zhao wrote:
> >>> +
> >>> +Groups:
> >>> + KVM_DEV_ARM_PMU_GRP_IRQ
> >>> + Attributes:
> >>> +The attr field of kvm_device_attr encodes one value:
> >>> +bits:
patch summary nit: s/typer/type/
Thanks,
drew
On Tue, Dec 22, 2015 at 04:08:03PM +0800, Shannon Zhao wrote:
> From: Shannon Zhao
>
> These kind of registers include PMEVTYPERn, PMCCFILTR and PMXEVTYPER
> which is mapped to PMEVTYPERn or PMCCFILTR.
>
> The access
On Fri, Jan 08, 2016 at 10:53:03AM +0800, Shannon Zhao wrote:
>
>
> On 2016/1/8 4:18, Andrew Jones wrote:
> > On Tue, Dec 22, 2015 at 04:08:15PM +0800, Shannon Zhao wrote:
> >> From: Shannon Zhao <shannon.z...@linaro.org>
> >>
> >> Add a new kvm
On Thu, Jan 07, 2016 at 09:03:36AM +, Marc Zyngier wrote:
> At the moment, our fault injection is pretty limited. We always
> generate a SYNC exception into EL1, as if the fault was actually
> from EL1h, no matter how it was generated.
>
> This is obviously wrong, as EL0 can generate faults
Allow a thread to wait some specified amount of time. Can
specify in cycles, usecs, and msecs.
Signed-off-by: Andrew Jones <drjo...@redhat.com>
---
lib/arm/asm/processor.h | 19 +++
lib/arm/processor.c | 15 +++
lib/arm64/asm/processor.
Allow user to select who sends ipis and with which irq,
rather than just always sending irq=0 from cpu0.
Signed-off-by: Andrew Jones <drjo...@redhat.com>
---
v2: actually check that the irq received was the irq sent,
and (for gicv2) that the sender is the expected one.
---
arm/gic.
Signed-off-by: Andrew Jones <drjo...@redhat.com>
---
v2: configure irqs as NS GRP1
---
lib/arm/asm/arch_gicv3.h | 184 ++
lib/arm/asm/gic-v3.h | 321 +
lib/arm/asm/gic.h | 1 +
lib/arm/gic.c
Signed-off-by: Andrew Jones <drjo...@redhat.com>
---
arm/run | 19 ---
arm/selftest.c| 5 -
lib/arm/asm/processor.h | 9 +++--
lib/arm/asm/setup.h | 4 ++--
lib/arm/setup.c | 12 +++-
lib/arm64/asm/processor.
Signed-off-by: Andrew Jones <drjo...@redhat.com>
---
lib/arm/asm/processor.h | 10 ++
lib/arm64/asm/processor.h | 10 ++
2 files changed, 20 insertions(+)
diff --git a/lib/arm/asm/processor.h b/lib/arm/asm/processor.h
index afc903ca7d4ab..75a8d08b89330 100644
--- a/lib/a
Signed-off-by: Andrew Jones <drjo...@redhat.com>
---
v2: add more details in the output if a test fails,
report spurious interrupts if we get them
---
arm/Makefile.common | 6 +-
arm/gic.c | 194
arm/unittests.cfg | 7
Signed-off-by: Andrew Jones <drjo...@redhat.com>
---
lib/libcflat.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/lib/libcflat.h b/lib/libcflat.h
index 582e3fc60e287..e5e588c742763 100644
--- a/lib/libcflat.h
+++ b/lib/libcflat.h
@@ -27,8 +27,8 @@
#define __
unit test), currently just IPI
Available here: https://github.com/rhdrjones/kvm-unit-tests/commits/arm/gic
Andrew Jones (10):
lib: xstr: allow multiple args
arm64: fix get_"sysreg32" and make MPIDR 64bit
arm/arm64: smp: support more than 8 cpus
arm/arm64: add some delay routin
mrs is always 64bit, so we should always use a 64bit register.
Sometimes we'll only want to return the lower 32, but not for
MPIDR, as that does define fields in the upper 32.
Signed-off-by: Andrew Jones <drjo...@redhat.com>
---
lib/arm64/asm/processor.h | 15 +--
1 file chan
Add some gicv2 support. This just adds init and enable
functions, allowing unit tests to start messing with it.
Signed-off-by: Andrew Jones <drjo...@redhat.com>
---
arm/Makefile.common| 1 +
lib/arm/asm/gic-v2.h | 74 ++
lib/arm/asm
On Tue, Jun 07, 2016 at 06:13:53PM +0100, Alex Bennée wrote:
>
> Alex Bennée <alex.ben...@linaro.org> writes:
>
> > Andrew Jones <drjo...@redhat.com> writes:
> >
> >> v2:
> >> Rebased on on latest master + my "populate argv[0]" se
On Mon, Jun 06, 2016 at 11:49:09AM +0100, Alex Bennée wrote:
>
> Andrew Jones <drjo...@redhat.com> writes:
>
> > Signed-off-by: Andrew Jones <drjo...@redhat.com>
> > ---
> > lib/libcflat.h | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions
On Mon, Jun 06, 2016 at 05:22:49PM +0100, Alex Bennée wrote:
>
> Andrew Jones <drjo...@redhat.com> writes:
>
> > Signed-off-by: Andrew Jones <drjo...@redhat.com>
> > ---
> > arm/run | 19 ---
> > arm/selftest.c
On Mon, Jun 06, 2016 at 06:39:50PM +0100, Alex Bennée wrote:
>
> Andrew Jones <drjo...@redhat.com> writes:
>
> > Allow a thread to wait some specified amount of time. Can
> > specify in cycles, usecs, and msecs.
>
> I wonder if delay() and mdelay() can be in
Hi Ard,
Thanks for bringing this back up again (I think :-)
On Fri, Jun 24, 2016 at 04:04:45PM +0200, Ard Biesheuvel wrote:
> Hi all,
>
> This old subject came up again in a discussion related to PCIe support
> for QEMU/KVM under Tianocore. The fact that we need to map PCI MMIO
> regions as
On Sat, Jan 09, 2016 at 03:03:39PM +, Marc Zyngier wrote:
> On Sat, 9 Jan 2016 13:29:56 +0100
> Christoffer Dall <christoffer.d...@linaro.org> wrote:
>
> > On Thu, Jan 07, 2016 at 09:36:47PM +0100, Andrew Jones wrote:
> > > On Thu, Jan 07, 2016 at 02:56:1
te:
> >>
> >>>> On Thu, Jan 07, 2016 at 09:36:47PM +0100, Andrew Jones wrote:
> >>>>>> On Thu, Jan 07, 2016 at 02:56:15PM +, Peter Maydell wrote:
> >>>>>>>> On 7 January 2016 at 14:49, Shannon Zhao <zhaoshengl...
On Mon, Jan 11, 2016 at 04:29:03PM +, Peter Maydell wrote:
> On 11 January 2016 at 16:21, Andrew Jones <drjo...@redhat.com> wrote:
> > On Mon, Jan 11, 2016 at 05:09:27PM +0100, Andrew Jones wrote:
> >> On Mon, Jan 11, 2016 at 04:09:29PM +0100, Christoffer Dall wr
On Mon, Jan 11, 2016 at 04:09:29PM +0100, Christoffer Dall wrote:
> On Mon, Jan 11, 2016 at 03:07:17PM +0100, Andrew Jones wrote:
> > On Sat, Jan 09, 2016 at 03:03:39PM +, Marc Zyngier wrote:
> > > On Sat, 9 Jan 2016 13:29:56 +0100
> > > Christoffer Dall <chri
On Fri, Jan 15, 2016 at 02:27:55PM +0800, Shannon Zhao wrote:
> From: Shannon Zhao
>
> To configure the virtual PMUv3 overflow interrupt number, we use the
> vcpu kvm_device ioctl, encapsulating the KVM_ARM_VCPU_PMU_V3_IRQ
> attribute within the KVM_ARM_VCPU_PMU_V3_CTRL
ne the respective ioctls
> for the vcpu file descriptor.
>
> Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
> ---
> CC: Peter Maydell <peter.mayd...@linaro.org>
> ---
Reviewed-by: Andrew Jones <drjo...@redhat.com>
__
the bus number too, but I'm not sure it's
necessary for simple kvm-unit-tests.
>
> Cc: Andrew Jones <drjo...@redhat.com>
> Signed-off-by: Alexander Gordeev <agord...@redhat.com>
> ---
> lib/pci-host-generic.c | 54
>
On Fri, Jan 15, 2016 at 02:27:34PM +0800, Shannon Zhao wrote:
> From: Shannon Zhao
...
> This patchset can be fetched from [1] and the relevant QEMU version for
> test can be fetched from [2].
>
...
> [1] https://git.linaro.org/people/shannon.zhao/linux-mainline.git
>
On Sat, Jan 09, 2016 at 01:22:47PM +0100, Alexander Gordeev wrote:
> This series extends the kvm-unit-tests/arm framework to support PCI.
>
> Cc: Andrew Jones <drjo...@redhat.com>
>
> Alexander Gordeev (11):
> arm/pci: Device tree PCI probing
> arm/pci: PCI bus
On Sat, Jan 09, 2016 at 01:22:54PM +0100, Alexander Gordeev wrote:
> Cc: Andrew Jones <drjo...@redhat.com>
> Signed-off-by: Alexander Gordeev <agord...@redhat.com>
> ---
> arm/pci-test.c| 2 +-
> lib/pci-testdev.c | 139
> +
On Sat, Jan 09, 2016 at 01:22:56PM +0100, Alexander Gordeev wrote:
> Cc: Andrew Jones <drjo...@redhat.com>
> Signed-off-by: Alexander Gordeev <agord...@redhat.com>
> ---
> lib/pci-host-generic.c | 35 +++
> 1 file changed, 35 insertions(+
On Sat, Jan 09, 2016 at 01:22:58PM +0100, Alexander Gordeev wrote:
> Cc: Andrew Jones <drjo...@redhat.com>
> Signed-off-by: Alexander Gordeev <agord...@redhat.com>
> ---
> lib/pci-testdev.c | 18 ++
> 1 file changed, 18 insertions(+)
>
> diff --
On Sat, Jan 09, 2016 at 01:22:57PM +0100, Alexander Gordeev wrote:
> Cc: Andrew Jones <drjo...@redhat.com>
> Signed-off-by: Alexander Gordeev <agord...@redhat.com>
> ---
> lib/pci-host-generic.c | 34 ++
> 1 file changed, 34 insertions(+
On Sat, Jan 09, 2016 at 01:22:55PM +0100, Alexander Gordeev wrote:
> Cc: Andrew Jones <drjo...@redhat.com>
> Signed-off-by: Alexander Gordeev <agord...@redhat.com>
> ---
> lib/pci-testdev.c | 16
> 1 file changed, 16 insertions(+)
>
> diff --
On Sat, Jan 09, 2016 at 01:22:49PM +0100, Alexander Gordeev wrote:
> Scan bus 0 and function 0 only for now
>
> Cc: Andrew Jones <drjo...@redhat.com>
> Signed-off-by: Alexander Gordeev <agord...@redhat.com>
> ---
> arm/pci-test.c | 4 +++
On Sat, Jan 09, 2016 at 01:22:48PM +0100, Alexander Gordeev wrote:
> Cc: Andrew Jones <drjo...@redhat.com>
> Signed-off-by: Alexander Gordeev <agord...@redhat.com>
> ---
> arm/pci-test.c | 25 +++
> config/config-arm-common.mak | 5 +-
> lib/
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