On 19 September 2016 at 08:36, Vijay Kilari wrote:
> In order to track the PRI and ID bits written by guest,
> VGIC needs to store these values when ICC_CTRL_EL1 is updated.
> However, QEMU is reseting VGIC by writing 0's to all the
> registers after VGIC initialization and hence the back up valu
Hi Marc , Peter
On Sat, Sep 17, 2016 at 5:07 PM, Marc Zyngier wrote:
> On Sat, 17 Sep 2016 11:58:48 +0530
> Vijay Kilari wrote:
>
>> On Fri, Sep 16, 2016 at 10:37 PM, Marc Zyngier wrote:
>> > On 16/09/16 17:57, Vijay Kilari wrote:
>> >> On Fri, Sep 16, 2016 at 8:06 PM, Marc Zyngier
>> >> wrot
On Sun, 18 Sep 2016 12:00:01 +0530
Vijay Kilari wrote:
> Hi Marc,
>
> On Fri, Sep 16, 2016 at 10:37 PM, Marc Zyngier wrote:
> > On 16/09/16 17:57, Vijay Kilari wrote:
> >> On Fri, Sep 16, 2016 at 8:06 PM, Marc Zyngier
> >> wrote:
> >>> On 16/09/16 13:20, vijay.kil...@gmail.com wrote:
>
Hi Marc,
On Fri, Sep 16, 2016 at 10:37 PM, Marc Zyngier wrote:
> On 16/09/16 17:57, Vijay Kilari wrote:
>> On Fri, Sep 16, 2016 at 8:06 PM, Marc Zyngier wrote:
>>> On 16/09/16 13:20, vijay.kil...@gmail.com wrote:
From: Vijaya Kumar K
VGICv3 CPU interface registers are accessed us
On Sat, 17 Sep 2016 11:58:48 +0530
Vijay Kilari wrote:
> On Fri, Sep 16, 2016 at 10:37 PM, Marc Zyngier wrote:
> > On 16/09/16 17:57, Vijay Kilari wrote:
> >> On Fri, Sep 16, 2016 at 8:06 PM, Marc Zyngier
> >> wrote:
> >>> On 16/09/16 13:20, vijay.kil...@gmail.com wrote:
> From: Vij
On Fri, Sep 16, 2016 at 10:37 PM, Marc Zyngier wrote:
> On 16/09/16 17:57, Vijay Kilari wrote:
>> On Fri, Sep 16, 2016 at 8:06 PM, Marc Zyngier wrote:
>>> On 16/09/16 13:20, vijay.kil...@gmail.com wrote:
From: Vijaya Kumar K
VGICv3 CPU interface registers are accessed using
K
On 16/09/16 17:57, Vijay Kilari wrote:
> On Fri, Sep 16, 2016 at 8:06 PM, Marc Zyngier wrote:
>> On 16/09/16 13:20, vijay.kil...@gmail.com wrote:
>>> From: Vijaya Kumar K
>>>
>>> VGICv3 CPU interface registers are accessed using
>>> KVM_DEV_ARM_VGIC_CPU_SYSREGS ioctl. These registers are accessed
On Fri, Sep 16, 2016 at 8:06 PM, Marc Zyngier wrote:
> On 16/09/16 13:20, vijay.kil...@gmail.com wrote:
>> From: Vijaya Kumar K
>>
>> VGICv3 CPU interface registers are accessed using
>> KVM_DEV_ARM_VGIC_CPU_SYSREGS ioctl. These registers are accessed
>> as 64-bit. The cpu MPIDR value is passed a
On 16/09/16 13:20, vijay.kil...@gmail.com wrote:
> From: Vijaya Kumar K
>
> VGICv3 CPU interface registers are accessed using
> KVM_DEV_ARM_VGIC_CPU_SYSREGS ioctl. These registers are accessed
> as 64-bit. The cpu MPIDR value is passed along with register id.
> is used to identify the cpu for reg
From: Vijaya Kumar K
VGICv3 CPU interface registers are accessed using
KVM_DEV_ARM_VGIC_CPU_SYSREGS ioctl. These registers are accessed
as 64-bit. The cpu MPIDR value is passed along with register id.
is used to identify the cpu for registers access.
The version of VGIC v3 specification is defin
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