Hi guys,
On 30/06/2020 09:36, Will Deacon wrote:
> On Tue, Jun 30, 2020 at 09:15:15AM +0100, Marc Zyngier wrote:
>> On 2020-06-29 22:33, Rob Herring wrote:
>>> On Cortex-A77 r0p0 and r1p0, a sequence of a non-cacheable or device
>>> load
>>> and a store exclusive or PAR_EL1 read can cause a
[+Jose]
On Tue, Jun 30, 2020 at 09:15:15AM +0100, Marc Zyngier wrote:
> On 2020-06-29 22:33, Rob Herring wrote:
> > On Cortex-A77 r0p0 and r1p0, a sequence of a non-cacheable or device
> > load
> > and a store exclusive or PAR_EL1 read can cause a deadlock.
> >
> > The workaround requires a DMB
Hi Rob,
On 2020-06-29 22:33, Rob Herring wrote:
On Cortex-A77 r0p0 and r1p0, a sequence of a non-cacheable or device
load
and a store exclusive or PAR_EL1 read can cause a deadlock.
The workaround requires a DMB SY before and after a PAR_EL1 register
read
and the disabling of KVM. KVM must
