Re: [PATCH v4] arm64: Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC

2018-02-22 Thread Robin Murphy
On 22/02/18 16:33, Mark Rutland wrote: On Thu, Feb 22, 2018 at 04:28:03PM +, Robin Murphy wrote: [Apologies to keep elbowing in, and if I'm being thick here...] On 22/02/18 15:22, Mark Rutland wrote: On Thu, Feb 22, 2018 at 08:51:30AM -0600, Shanker Donthineni wrote: +#define

Re: [PATCH v4] arm64: Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC

2018-02-22 Thread Mark Rutland
On Thu, Feb 22, 2018 at 04:28:03PM +, Robin Murphy wrote: > [Apologies to keep elbowing in, and if I'm being thick here...] > > On 22/02/18 15:22, Mark Rutland wrote: > > On Thu, Feb 22, 2018 at 08:51:30AM -0600, Shanker Donthineni wrote: > > > +#define CTR_B31_SHIFT31 > > > >

Re: [PATCH v4] arm64: Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC

2018-02-22 Thread Robin Murphy
[Apologies to keep elbowing in, and if I'm being thick here...] On 22/02/18 15:22, Mark Rutland wrote: On Thu, Feb 22, 2018 at 08:51:30AM -0600, Shanker Donthineni wrote: +#define CTR_B31_SHIFT 31 Since this is just a RES1 bit, I think we don't need a mnemonic for it, but I'll defer

Re: [PATCH v4] arm64: Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC

2018-02-22 Thread Mark Rutland
On Thu, Feb 22, 2018 at 08:51:30AM -0600, Shanker Donthineni wrote: > +#define CTR_B31_SHIFT31 Since this is just a RES1 bit, I think we don't need a mnemonic for it, but I'll defer to Will and Catalin on that. > ENTRY(invalidate_icache_range) > +#ifdef