Re: [PATCH v6] arm64: Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC

2018-03-07 Thread Will Deacon
On Tue, Mar 06, 2018 at 01:33:00PM -0600, Shanker Donthineni wrote: > > I also confirmed with Thomas Speier, we can skip __flush_icache_all() if > > DIC=1. Thanks, > Planning to patch __flush_icache_all() itself instead of changing the > callers. This > way we can avoid "ic ialluis" completely.

Re: [PATCH v6] arm64: Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC

2018-03-06 Thread Shanker Donthineni
Hi Will, On 03/06/2018 12:48 PM, Shanker Donthineni wrote: > Hi Will, > > On 03/06/2018 09:23 AM, Will Deacon wrote: >> Hi Shanker, >> >> On Tue, Mar 06, 2018 at 08:47:27AM -0600, Shanker Donthineni wrote: >>> On 03/06/2018 07:44 AM, Will Deacon wrote: I think this is a slight asymmetry with

Re: [PATCH v6] arm64: Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC

2018-03-06 Thread Shanker Donthineni
Hi Will, On 03/06/2018 09:23 AM, Will Deacon wrote: > Hi Shanker, > > On Tue, Mar 06, 2018 at 08:47:27AM -0600, Shanker Donthineni wrote: >> On 03/06/2018 07:44 AM, Will Deacon wrote: >>> I think this is a slight asymmetry with the code for the I-side. On the >>> I-side, you hook into invalidate_

Re: [PATCH v6] arm64: Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC

2018-03-06 Thread Will Deacon
Hi Shanker, On Tue, Mar 06, 2018 at 08:47:27AM -0600, Shanker Donthineni wrote: > On 03/06/2018 07:44 AM, Will Deacon wrote: > > I think this is a slight asymmetry with the code for the I-side. On the > > I-side, you hook into invalidate_icache_by_line, whereas on the D-side you > > hook into the

Re: [PATCH v6] arm64: Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC

2018-03-06 Thread Shanker Donthineni
Hi Will On 03/06/2018 07:44 AM, Will Deacon wrote: > Hi Shanker, > > On Wed, Feb 28, 2018 at 10:14:00PM -0600, Shanker Donthineni wrote: >> The DCache clean & ICache invalidation requirements for instructions >> to be data coherence are discoverable through new fields in CTR_EL0. >> The following

Re: [PATCH v6] arm64: Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC

2018-03-06 Thread Robin Murphy
On 01/03/18 04:14, Shanker Donthineni wrote: [...] diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 2985a06..0b64b55 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -199,12 +199,12 @@ static int __init register_cpu_hwcaps_dumpe

Re: [PATCH v6] arm64: Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC

2018-03-06 Thread Will Deacon
Hi Shanker, On Wed, Feb 28, 2018 at 10:14:00PM -0600, Shanker Donthineni wrote: > The DCache clean & ICache invalidation requirements for instructions > to be data coherence are discoverable through new fields in CTR_EL0. > The following two control bits DIC and IDC were defined for this > purpose