On Thu Mar 08, 2018 at 00:52:55 +0100, Paul Boddie wrote:
> On Wednesday 7. March 2018 01.22.46 Paul Boddie wrote:
> >
> > Currently, I have reason to believe that an exception occurs causing the
> > sigma0 thread to terminate, but it's getting late and my debugging
> > efficiency is suffering. I
On Wednesday 7. March 2018 01.22.46 Paul Boddie wrote:
>
> Currently, I have reason to believe that an exception occurs causing the
> sigma0 thread to terminate, but it's getting late and my debugging
> efficiency is suffering. I think that when the thread terminates, it has
> the following cause
On Wednesday 7. March 2018 00.27.34 Adam Lackorzynski wrote:
>
> The asm code sets cp0_status upon exit which includes enabling
> interrupts. Are you sure you're not getting any timer interrupts when
> supposedly running inside sigma0? (Flipping some pixels in the timer
> handler...)
You beat to
On Tue Mar 06, 2018 at 01:14:25 +0100, Paul Boddie wrote:
> On Tuesday 6. March 2018 00.46.29 Adam Lackorzynski wrote:
> >
> > All what you write sounds good. In any case the eret must restore state
> > including setting the right interrupt state. Are you getting timer
> > interrupts when sigma0
On Tuesday 6. March 2018 00.46.29 Adam Lackorzynski wrote:
>
> All what you write sounds good. In any case the eret must restore state
> including setting the right interrupt state. Are you getting timer
> interrupts when sigma0 shall run, or is there silence? Is ESC working to
> get into jdb?
Th
Hi Paul,
On Sun Mar 04, 2018 at 22:25:12 +0100, Paul Boddie wrote:
> I've been trying to coerce L4Re and Fiasco.OC to work with the Ben NanoNote,
> which is related to the MIPS Creator CI20 that is (mostly - see earlier
> discussions) supported by this software. There are a few challenges involv
