Re: fiasco.oc i.MX7d port

[Adam Lackorzynski]

Hi,

On Fri Oct 14, 2016 at 11:03:16 +0200, Marc CHALAND wrote:
> OK, I see. My #ifndef was not good. Seems to work now. I've got the CPU[1]
> goes to idle loop :). If you wish, I can send to you the patch to get it
> work ?

Good it works now. Please don't bother, I'll take care of that. :)


Adam

> Le jeudi 13 octobre 2016, Adam Lackorzynski  a
> écrit :
> 
> > Hi Marc,
> >
> > On Wed Oct 12, 2016 at 11:17:36 +0200, Marc CHALAND wrote:
> > > Le mercredi 12 octobre 2016, Adam Lackorzynski <
> > a...@os.inf.tu-dresden.de 
> > >  > > ');>>
> > a écrit :
> > > >
> > > > I do not see anything obviously wrong right away. I assume it passes
> > the
> > > > while loop?
> > > >
> > >
> > > Yes, the while loop exits. In fact, I think uboot powers up core1. I saw
> > > some piece of code. So I asserted that core1 starts on tramp func and I
> > saw
> > > that SCU was manipulated. But I don't understand what is done after.
> > > Perhaps it is not compatible with A7 and/or i.MX7 ?
> > > I've put a log into boot_ap_cpu() and it is not reached. Is there a way
> > to
> > > test if something is wrong between tramp_mp_entry and boot_ap_cpu() ?
> >
> > Ah, remove those few lines that flip that bit on the SCU. It's wrong
> > doing that on an A7. Or did you do that already?
> > In any case I'll get an i.MX7 in a few days so I can look myself if
> > still necessary.
> >
> >
> >
> >
> > Adam
> > --
> > Adam a...@os.inf.tu-dresden.de 
> >   Lackorzynski http://os.inf.tu-dresden.de/~adam/
> >
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> >

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Adam
-- 
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  Lackorzynski http://os.inf.tu-dresden.de/~adam/

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Re: fiasco.oc i.MX7d port

[Marc CHALAND]

OK, I see. My #ifndef was not good. Seems to work now. I've got the CPU[1]
goes to idle loop :). If you wish, I can send to you the patch to get it
work ?

Marc

Le jeudi 13 octobre 2016, Adam Lackorzynski  a
écrit :

> Hi Marc,
>
> On Wed Oct 12, 2016 at 11:17:36 +0200, Marc CHALAND wrote:
> > Le mercredi 12 octobre 2016, Adam Lackorzynski <
> a...@os.inf.tu-dresden.de 
> > ');>>
> a écrit :
> > >
> > > I do not see anything obviously wrong right away. I assume it passes
> the
> > > while loop?
> > >
> >
> > Yes, the while loop exits. In fact, I think uboot powers up core1. I saw
> > some piece of code. So I asserted that core1 starts on tramp func and I
> saw
> > that SCU was manipulated. But I don't understand what is done after.
> > Perhaps it is not compatible with A7 and/or i.MX7 ?
> > I've put a log into boot_ap_cpu() and it is not reached. Is there a way
> to
> > test if something is wrong between tramp_mp_entry and boot_ap_cpu() ?
>
> Ah, remove those few lines that flip that bit on the SCU. It's wrong
> doing that on an A7. Or did you do that already?
> In any case I'll get an i.MX7 in a few days so I can look myself if
> still necessary.
>
>
>
>
> Adam
> --
> Adam a...@os.inf.tu-dresden.de 
>   Lackorzynski http://os.inf.tu-dresden.de/~adam/
>
> ___
> l4-hackers mailing list
> l4-hackers@os.inf.tu-dresden.de 
> http://os.inf.tu-dresden.de/mailman/listinfo/l4-hackers
>
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Re: fiasco.oc i.MX7d port

[Adam Lackorzynski]

Hi Marc,

On Wed Oct 12, 2016 at 11:17:36 +0200, Marc CHALAND wrote:
> Le mercredi 12 octobre 2016, Adam Lackorzynski  > a écrit :
> >
> > I do not see anything obviously wrong right away. I assume it passes the
> > while loop?
> >
> 
> Yes, the while loop exits. In fact, I think uboot powers up core1. I saw
> some piece of code. So I asserted that core1 starts on tramp func and I saw
> that SCU was manipulated. But I don't understand what is done after.
> Perhaps it is not compatible with A7 and/or i.MX7 ?
> I've put a log into boot_ap_cpu() and it is not reached. Is there a way to
> test if something is wrong between tramp_mp_entry and boot_ap_cpu() ?

Ah, remove those few lines that flip that bit on the SCU. It's wrong
doing that on an A7. Or did you do that already?
In any case I'll get an i.MX7 in a few days so I can look myself if
still necessary.




Adam
-- 
Adam a...@os.inf.tu-dresden.de
  Lackorzynski http://os.inf.tu-dresden.de/~adam/

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fiasco.oc i.MX7d port

[Marc CHALAND]

Le mercredi 12 octobre 2016, Adam Lackorzynski > a écrit :
>
> I do not see anything obviously wrong right away. I assume it passes the
> while loop?
>

Yes, the while loop exits. In fact, I think uboot powers up core1. I saw
some piece of code. So I asserted that core1 starts on tramp func and I saw
that SCU was manipulated. But I don't understand what is done after.
Perhaps it is not compatible with A7 and/or i.MX7 ?
I've put a log into boot_ap_cpu() and it is not reached. Is there a way to
test if something is wrong between tramp_mp_entry and boot_ap_cpu() ?
Regards
Marc
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fiasco.oc i.MX7d port

[Marc CHALAND]

platform_control-arm-imx7.cpp


Hi Adam :)

Le samedi 8 octobre 2016, Adam Lackorzynski > a écrit :

> Hi,
>
> On Wed Oct 05, 2016 at 19:50:45 +0200, Marc CHALAND wrote:
>
> > So, I ifdefed it but CPU0 still doesn't startup. Can somebody help me ?
>
> You mean CPU1? Did you also add different setting for SCR? It seems to
> be different for imx7.
>

Yes, I mean CPU1. I created a file platform_control-arm-imx7.cpp which sets
power up on CPU1 through GPC registers, sets tramp addr into SRC registers
and enables CORE1 like linux does.  See attachment.
Regards
Marc
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Re: fiasco.oc i.MX7d port

[Adam Lackorzynski]

Hi,

On Wed Oct 05, 2016 at 19:50:45 +0200, Marc CHALAND wrote:
> I'm trying to port fiasco.oc to i.MX7d. It works, but I cannot start second
> core. I set trampoline addr into corresponding GPR and enables CORE1. But
> nothing happens. I saw that trampoline assembler code enables SCU through
> external registers. But with cortex a7, SCU hasn't got external registers.

Yes, must not be done on A7. Disabling this block should be sufficient
regarding the SCU.

> So, I ifdefed it but CPU0 still doesn't startup. Can somebody help me ?

You mean CPU1? Did you also add different setting for SCR? It seems to
be different for imx7.



Adam
-- 
Adam a...@os.inf.tu-dresden.de
  Lackorzynski http://os.inf.tu-dresden.de/~adam/

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fiasco.oc i.MX7d port

[Marc CHALAND]

Hi,
I'm trying to port fiasco.oc to i.MX7d. It works, but I cannot start second
core. I set trampoline addr into corresponding GPR and enables CORE1. But
nothing happens. I saw that trampoline assembler code enables SCU through
external registers. But with cortex a7, SCU hasn't got external registers.
So, I ifdefed it but CPU0 still doesn't startup. Can somebody help me ?
Regards
Marc
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