On May 12, 2014, at 2:47 PM, Marcin Jurczuk wrote:
> I will look if this is possible to get such behavior with DMA. Within
> spi1_isr() I just check counter of send packets after BSY is clear.
> Previous solution with TXE flag wasn't working since TXE flag is set but in
> the meantime data tra
That was the exact same issue I was seeing and hence my non-use of DMA
(also need to switch the command/data signal mid transmission.
Patches can be submitted to the github repo
https://github.com/libopencm3/libopencm3
--Chuck
On Mon, May 12, 2014 at 2:47 PM, Marcin Jurczuk wrote:
> I know a
I know about DMA however I need exactly information when data are really
send not only when SPI TX buffer is empty.
Here is sample two transmissions:
http://www.zimagez.com/zimage/screenshot-12052014-233910.php
First line is CE latch low pulse
Second is SCK
Third line are data.
LATCH (CE LOW) must
IME, it's better to use DMA and then poll BSY in your DMA completion handler,
since it will never stay set for more than one byte time. (Assuming the
transfer is large enough to justify not simply polling).
= Mike
On May 12, 2014, at 9:13 AM, Chuck McManis wrote:
> Yes, many people have dis
Yes, many people have discovered the almost useless implementation of SPI
by SM. I built a driver for an LCD display and used the hack of counting
receive interrupts to know when it would be 'safe' to take my CS pin high.
If you look at the STM32F429 branch of my libopencm3-examples repo on
Github[
You re right,
They are almost useless. Thing is that LCD is driven "spi like". I need to
fill 112 bit shift register a then latch data using CS low level pulse.
I used BSY flag inside spi1_isr() after 14 bytes send to latch data, and
this solution works perfectly.
Funny think is that when you (
