[Libva] [PATCH V3 5/9] ENC: add AVC common structure and functions

v1:add kernel pointer for different platform Signed-off-by: Pengfei Qu <pengfei...@intel.com> Reviewed-by: Sean V Kelley<sea...@posteo.de> --- src/Makefile.am | 2 + src/i965_avc_encoder_common.c | 319 ++ src/i965_avc_enco

[Libva] [PATCH V3 8/9] ENC: add MFX pipeline for AVC encoder

MFX pipeline: add MFX command for AVC encoder add MFX Picture slice level command init for AVC add MFX pipeline init prepare run for AVC encode add VME/MFX context init for AVC encoder Reviewed-by: Sean V Kelley<sea...@posteo.de> Signed-off-by: Pengfei Qu <pengfei...@intel.com&

[Libva] [PATCH V3 2/9] ENC: add common structure for AVC/HEVC encoder

v1: add context init function for AVC encoder v2: add file in the Makefile.am Signed-off-by: Pengfei Qu <pengfei...@intel.com> Reviewed-by: Sean V Kelley<sea...@posteo.de> --- src/Makefile.am | 3 + src/i965_encoder_api.h| 47 + src/i965_encoder_co

[Libva] [PATCH V3 6/9] ENC: add kernel related structure and define for AVC

Signed-off-by: Pengfei Qu <pengfei...@intel.com> Reviewed-by: Sean V Kelley<sea...@posteo.de> --- src/Makefile.am|1 + src/gen9_avc_encoder.h | 2339 2 files changed, 2340 insertions(+) create mode 100644 src/gen9_avc_enc

[Libva] [PATCH V3 0/9] Encoder Architecture Changes (Primarily AVC)

: rebase to lastest master branch and use i965->intel->media_mocs to configure the memory MOCS. remove unused enum value Pengfei Qu (9): ENC: move gpe related function into src/i965_gpe_utils.h/c ENC: add common structure for AVC/HEVC encoder ENC: add const data/table for AVC encoder

[Libva] [PATCH V3 9/9] ENC:support more quality level and switch to new AVC encoder solution on SKL/APL

v1: add AVC encoder support on APL Signed-off-by: Pengfei Qu <pengfei...@intel.com> Reviewed-by: Sean V Kelley<sea...@posteo.de> --- src/gen9_avc_encoder.c | 3 ++- src/i965_drv_video.c | 8 ++-- src/i965_drv_video.h | 2 ++ src/i965_encode

[Libva] [PATCH V3 1/9] ENC: move gpe related function into src/i965_gpe_utils.h/c

v1: add align version for obj surface conversion to gpe surface remove comments and enum value v2: use intel->media_mocs to configure the memory property Signed-off-by: Pengfei Qu <pengfei...@intel.com> Reviewed-by: Sean V Kelley<sea...@posteo.de> --- src/gen9_vp9_

[Libva] [PATCH V3 3/9] ENC: add const data/table for AVC encoder

v1： add fies in the Makefile.am Signed-off-by: Pengfei Qu <pengfei...@intel.com> Reviewed-by: Sean V Kelley<sea...@posteo.de> --- src/Makefile.am |2 + src/gen9_avc_const_def.c | 1090 ++ src/gen9_avc_const_def.h | 115 ++

[Libva] [PATCH v2 5/9] ENC: add AVC common structure and functions

v1:add kernel pointer for different platform Signed-off-by: Pengfei Qu <pengfei...@intel.com> Reviewed-by: Sean V Kelley<sea...@posteo.de> --- src/Makefile.am | 2 + src/i965_avc_encoder_common.c | 319 ++ src/i965_avc_enco

[Libva] [PATCH v2 8/9] ENC: add MFX pipeline for AVC encoder

MFX pipeline: add MFX command for AVC encoder add MFX Picture slice level command init for AVC add MFX pipeline init prepare run for AVC encode add VME/MFX context init for AVC encoder Reviewed-by: Sean V Kelley<sea...@posteo.de> Signed-off-by: Pengfei Qu <pengfei...@intel.com&

[Libva] [PATCH v2 9/9] ENC:support more quality level and switch to new AVC encoder solution on SKL/APL

v1: add AVC encoder support on APL Signed-off-by: Pengfei Qu <pengfei...@intel.com> Reviewed-by: Sean V Kelley<sea...@posteo.de> --- src/gen9_avc_encoder.c | 5 +++-- src/i965_drv_video.c | 8 ++-- src/i965_drv_video.h | 2 ++ src/i965_encode

[Libva] [PATCH v2 1/9] ENC: move gpe related function into src/i965_gpe_utils.h/c

v1: add align version for obj surface conversion to gpe surface remove comments and enum value Signed-off-by: Pengfei Qu <pengfei...@intel.com> Reviewed-by: Sean V Kelley<sea...@posteo.de> --- src/gen9_vp9_encoder.c | 154 ++--- src/gen9_vp9_encoder.h |

[Libva] [PATCH v2 3/9] ENC: add const data/table for AVC encoder

v1： add fies in the Makefile.am Signed-off-by: Pengfei Qu <pengfei...@intel.com> Reviewed-by: Sean V Kelley<sea...@posteo.de> --- src/Makefile.am |2 + src/gen9_avc_const_def.c | 1090 ++ src/gen9_avc_const_def.h | 115 ++

[Libva] [PATCH v2 2/9] ENC: add common structure for AVC/HEVC encoder

v1: add context init function for AVC encoder v2: add file in the Makefile.am Signed-off-by: Pengfei Qu <pengfei...@intel.com> Reviewed-by: Sean V Kelley<sea...@posteo.de> --- src/Makefile.am | 3 + src/i965_encoder_api.h| 47 src/i965_encoder_co

[Libva] [PATCH v2 0/9] Encoder Architecture Changes (Primarily AVC)

. Pengfei Qu (9): ENC: move gpe related function into src/i965_gpe_utils.h/c ENC: add common structure for AVC/HEVC encoder ENC: add const data/table for AVC encoder ENC: add AVC kernel binary on SKL ENC: add AVC common structure and functions ENC: add kernel related structure and define

[Libva] [PATCH v1 9/9] ENC:support more quality level and switch to new AVC encoder solution on SKL

Signed-off-by: Pengfei Qu <pengfei...@intel.com> Reviewed-by: Sean V Kelley<sea...@posteo.de> --- src/Makefile.am | 10 ++ src/i965_drv_video.c | 8 ++-- src/i965_drv_video.h | 2 ++ src/i965_encoder.c | 52 4 f

[Libva] [PATCH v1 2/9] ENC: add common structure for AVC/HEVC encoder

add context init function for AVC encoder Signed-off-by: Pengfei Qu <pengfei...@intel.com> Reviewed-by: Sean V Kelley<sea...@posteo.de> --- src/i965_encoder_api.h| 47 src/i965_encoder_common.c | 124 +++ src/i965_encoder_co

[Libva] [PATCH v1 5/9] ENC: add AVC common structure and functions

v1:add kernel pointer for different platform Signed-off-by: Pengfei Qu <pengfei...@intel.com> Reviewed-by: Sean V Kelley<sea...@posteo.de> --- src/i965_avc_encoder_common.c | 319 ++ src/i965_avc_encoder_co

[Libva] [PATCH v1 6/9] ENC: add kernel related structure and define for AVC

Signed-off-by: Pengfei Qu <pengfei...@intel.com> Reviewed-by: Sean V Kelley<sea...@posteo.de> --- src/gen9_avc_encoder.h | 2339 1 file changed, 2339 insertions(+) create mode 100755 src/gen9_avc_encoder.h diff --git a/src/gen9_avc

[Libva] [PATCH v1 0/9]Encoder Architecture Changes (Primarily AVC)

Encoder architecture restructuring for H.264 (with some impact to HEVC now) on HSW+ * Improvements to the shaders * Improvements to the B frame efficiency * Improvements to the low bit rate mode * Improved features in two stage VME/PAK pipeline v1: Reduce the patch number and re org for VME and

[Libva] [PATCH] Fix: check the bo of reconstructed to ensure it is not NULL

Signed-off-by: Pengfei Qu <pengfei...@intel.com> --- src/gen9_vme.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/src/gen9_vme.c b/src/gen9_vme.c index 8cbe052..245b0df 100644 --- a/src/gen9_vme.c +++ b/src/gen9_vme.c @@ -1852,6 +1852,7 @@ static VAStatus gen9_intel_hevc_input

[Libva] [PATCH V4: 0/4] HEVC 10bit encoder enable

akui's comment Pengfei Qu (4): HEVC10bit ENC: add private surface for p010 conversion to nv12 HEVC10bit ENC:enable hevc 10bit on VME and PAK HEVC10bit ENC:enable hevc 10bit encoding pipeline HEVC10bit ENC: work around gpu hang when p010->nv12 src/gen6_mfc_common.c| 13 src/gen9_m

[Libva] [PATCH V4: 2/4] HEVC10bit ENC:enable hevc 10bit on VME and PAK

1.add p010->nv12 before VME 2.add CBR support Signed-off-by: Pengfei Qu <pengfei...@intel.com> --- src/gen6_mfc_common.c | 13 + src/gen9_mfc_hevc.c | 105 +- src/gen9_vme.c| 153 ++ 3 file

[Libva] [PATCH V4: 4/4] HEVC10bit ENC: work around gpu hang when p010->nv12

Signed-off-by: Pengfei Qu <pengfei...@intel.com> --- src/gen9_vme.c | 1 + src/i965_drv_video.h | 2 ++ 2 files changed, 3 insertions(+) diff --git a/src/gen9_vme.c b/src/gen9_vme.c index 8cbe052..4a7d932 100644 --- a/src/gen9_vme.c +++ b/src/gen9_vme.c @@ -1839,6 +1839,7 @@

[Libva] [PATCH V4: 1/4] HEVC10bit ENC: add private surface for p010 conversion to nv12

Signed-off-by: Pengfei Qu <pengfei...@intel.com> --- src/intel_media.h| 5 + src/intel_media_common.c | 7 +++ 2 files changed, 12 insertions(+) diff --git a/src/intel_media.h b/src/intel_media.h index 87d315f..4a55a93 100644 --- a/src/intel_media.h +++ b/src/intel_m

[Libva] [PATCH V4: 3/4] HEVC10bit ENC:enable hevc 10bit encoding pipeline

Signed-off-by: Pengfei Qu <pengfei...@intel.com> --- src/i965_device_info.c | 1 + src/i965_drv_video.c | 20 +++- src/i965_drv_video.h | 1 + src/i965_encoder.c | 18 +- 4 files changed, 30 insertions(+), 10 deletions(-) diff --git

[Libva] [PATCH V3: 1/4] HEVC10bit ENC: add private surface for p010 conversion to nv12

Signed-off-by: Pengfei Qu <pengfei...@intel.com> --- src/intel_media.h| 5 + src/intel_media_common.c | 10 ++ 2 files changed, 15 insertions(+) diff --git a/src/intel_media.h b/src/intel_media.h index 87d315f..4a55a93 100644 --- a/src/intel_media.h +++ b/src/intel_m

[Libva] [PATCH V3: 0/4] HEVC 10bit encoder enable

the series of patches enable the HEVC 10bit encoder on KBL+ v1: split the patch v2: move the internal surface member,which is used in p010->nv12, from VME context to gen_hevc_surface. move input surface conversion(p010->nv12) to vme prepare. Pengfei Qu (4): HEVC10bit ENC: add private s

[Libva] [PATCH V3: 2/4] HEVC10bit ENC:enable hevc 10bit on VME and PAK

1.add p010->nv12 before VME 2.add CBR support Signed-off-by: Pengfei Qu <pengfei...@intel.com> --- src/gen6_mfc_common.c | 13 + src/gen9_mfc_hevc.c | 105 ++-- src/gen9_vme.c| 146 ++ 3 file

[Libva] [PATCH V3: 4/4] HEVC10bit ENC: work around gpu hang when p010->nv12

Signed-off-by: Pengfei Qu <pengfei...@intel.com> --- src/gen9_vme.c | 1 + src/i965_drv_video.h | 2 ++ 2 files changed, 3 insertions(+) diff --git a/src/gen9_vme.c b/src/gen9_vme.c index 9e66275..264b27d 100644 --- a/src/gen9_vme.c +++ b/src/gen9_vme.c @@ -1839,6 +1839,7 @@

[Libva] [HEVC10bit ENC V2 1/5] HEVC10bit ENC: add driver context member and internal NV12 surface in VME

Signed-off-by: Pengfei Qu <pengfei...@intel.com> --- src/gen6_vme.c | 17 + src/gen6_vme.h | 8 src/gen7_vme.c | 2 ++ src/gen8_vme.c | 12 +++- 4 files changed, 38 insertions(+), 1 deletion(-) diff --git a/src/gen6_vme.c b/src/gen6_vme.c index 45cc30e..1

[Libva] [HEVC10bit ENC V2 2/5] HEVC ENC: 10bit support

this patch enable HEVC 10bit encoding on KBL+. v1: remove P010->NV12 for ref/reconstructed frame and enc frame from this patch remove call i965_SyncSurface to work around the GPU hang when 10bit->8bit(P010->NV12)from this patch Signed-off-by: Pengfei Qu <pengfei...@intel.c

[Libva] [HEVC10bit ENC V2 0/5] HEVC10bit encoder enable

the series of patches enable the HEVC 10bit encoder on KBL+ v1: split the patch move p010->nv12 to brc prepare for gen9 Pengfei Qu (5): HEVC10bit ENC: add driver context member and internal NV12 surface in VME HEVC ENC: 10bit support HEVC10bit:conver p010 to nv12 for ME surf

[Libva] [HEVC10bit ENC V2 4/5] HEVC10bit ENC: work around the gpu hang when convrt p010 to nv12

Signed-off-by: Pengfei Qu <pengfei...@intel.com> --- src/gen9_mfc_hevc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/gen9_mfc_hevc.c b/src/gen9_mfc_hevc.c index bc9225a..019dadf 100644 --- a/src/gen9_mfc_hevc.c +++ b/src/gen9_mfc_hevc.c @@ -2666,6 +2666,7 @@ static VA

[Libva] [HEVC10bit ENC V2 5/5] HEVC10 ENC: enable cbr

Signed-off-by: Pengfei Qu <pengfei...@intel.com> --- src/gen9_mfc_hevc.c | 8 1 file changed, 8 insertions(+) diff --git a/src/gen9_mfc_hevc.c b/src/gen9_mfc_hevc.c index 019dadf..f95d4f1 100644 --- a/src/gen9_mfc_hevc.c +++ b/src/gen9_mfc_hevc.c @@ -2279,6 +2279,14 @@ stati

[Libva] [HEVC10bit ENC V2 3/5] HEVC10bit:conver p010 to nv12 for ME surface

Signed-off-by: Pengfei Qu <pengfei...@intel.com> --- src/gen9_mfc_hevc.c | 127 1 file changed, 127 insertions(+) diff --git a/src/gen9_mfc_hevc.c b/src/gen9_mfc_hevc.c index 6021a7e..bc9225a 100644 --- a/src/gen9_mfc_hevc.c +++

[Libva] [PATCH 1/2] HEVC ENC: 10bit support

this patch enable HEVC 10bit encoding on KBL+. v1: add internal NV12 format surface in vme context structure. add VADriverContextP member in vem context structure. P010->NV12 is done in YUV check before encoding. v2: add P010->NV12 for ref/reconstructed frame and enc frame. v3: call

[Libva] [PATCH 2/2] HEVC10 ENC: enable cbr

--- src/gen9_mfc_hevc.c | 8 1 file changed, 8 insertions(+) diff --git a/src/gen9_mfc_hevc.c b/src/gen9_mfc_hevc.c index 6021a7e..ba48968 100644 --- a/src/gen9_mfc_hevc.c +++ b/src/gen9_mfc_hevc.c @@ -2279,6 +2279,14 @@ static void intel_hcpe_brc_init(struct encode_state

[Libva] [PATCH] Encoding: Add ROI example

ck v3: check the attrib return value for ROI Signed-off-by: Zhao Yakui <yakui.z...@intel.com> Signed-off-by: ceciliapeng <cecilia.p...@intel.com> Signed-off-by: Pengfei Qu <pengfei...@intel.com> --- test/encode/avcenc.c | 99 1 fil

[Libva] [PATCH 1/3] HEVC ENC:fill the correct chroma intra mode

Signed-off-by: Pengfei Qu <pengfei...@intel.com> --- src/gen9_mfc_hevc.c | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/src/gen9_mfc_hevc.c b/src/gen9_mfc_hevc.c index ad5e936..90b14bf 100644 --- a/src/gen9_mfc_hevc.c +++ b/src/gen9_mfc_hevc.c @@ -1246,15 +1

[Libva] [PATCH] Encoding: Add ROI example

Signed-off-by: Zhao Yakui <yakui.z...@intel.com> Signed-off-by: ceciliapeng <cecilia.p...@intel.com> Signed-off-by: Pengfei Qu <pengfei...@intel.com> --- test/encode/avcenc.c | 94 1 file changed, 88 insertions(+), 6 deletions(-) dif

[Libva] [PATCH V4: 03/11] encoding: Send VME instruction uses one register as the desc parameter

From: Zhao Yakui <yakui.z...@intel.com> The desc parameter of current VME send instruction is hardcode. And it can't be updated based on the input parameter. Signed-off-by: Zhao Yakui <yakui.z...@intel.com> Signed-off-by: pjl <cecilia.p...@intel.com> Signed-off-by: P

[Libva] [PATCH V4: 08/11] Encoding: ROI support for CQP/CBR on Haswell/Ivy

model to predicate the qp. (qp_value = intel_qpvalue_from_qp(qp)) Qp_value_roi * ROI_area + qp_value_nonroi * area_nonroi = base_qp * total_area. Signed-off-by: ceciliapeng <cecilia.p...@intel.com> Signed-off-by: Pengfei Qu <pengfei...@intel.com> --- src/gen6_

[Libva] [PATCH V4: 04/11] Encoding: Pass the qp parameter into VME shader and VME shader select the different cost table based on input Qp on Ivy

put Qp. Signed-off-by: Zhao Yakui <yakui.z...@intel.com> Signed-off-by: pjl <cecilia.p...@intel.com> Signed-off-by: Pengfei Qu <pengfei...@intel.com> --- src/gen6_mfc_common.c| 1 + src/gen7_vme.c | 155 +---

[Libva] [PATCH V4: 00/11]Add ROI feature on Gen7/Gen7.5/Gen8/Gen9 and scaling list features.

of motion vectors for B frame on HSW+ scaling matrix of h264 encoder on gen7/gen7.5/gen8/gen9 Pengfei Qu (1): ROI:enable on gen8 and gen9 Zhao Yakui (8): Encoding: mbmv cost table related changes for ROI Encoding: VME shader reads mbmv_cost from cost_table surface instead of constant

[Libva] [PATCH V4: 06/11] Encoding: Add one ROI flag and ROI buffer

Yakui <yakui.z...@intel.com> Signed-off-by: pjl <cecilia.p...@intel.com> Signed-off-by: Pengfei Qu <pengfei...@intel.com> --- src/gen6_mfc_common.c | 69 +++ src/gen6_vme.c| 3 +++ src/gen6_vme.h| 13 ++ sr

[Libva] [PATCH V4: 07/11] encoding:use the qp per every macroblock on Ivy and haswell

From: Zhao Yakui <yakui.z...@intel.com> v1: combine the patch together for Ivy and haswell use-CPU-to-construct-the-MFC-pak-command Signed-off-by: Zhao Yakui <yakui.z...@intel.com> Signed-off-by: ceciliapeng <cecilia.p...@intel.com> Signed-off-by: Pengfei Qu <pengfei..

[Libva] [PATCH V4: 05/11] Encoding: Dynamically select one mechanism to construct encoding command buffer for each frame on Haswell and Gen7/Gen6

ferent mechanism on the fly instead of statically compiled mode. Signed-off-by: Zhao Yakui <yakui.z...@intel.com> Signed-off-by: pjl <cecilia.p...@intel.com> Signed-off-by: Pengfei Qu <pengfei...@intel.com> --- src/gen6_mfc.c | 12 src/gen6_mfc.h | 1 -

[Libva] [PATCH V4: 09/11] ROI:enable on gen8 and gen9

v2: use ASSERT_RET to check the ROI flag setted by user. instead of assert. v1: ROI enable on gen8 and gen9 Enable GPU to construct GPU command under ROI scenario fix roi attrib config incorrectly Signed-off-by: Zhao Yakui <yakui.z...@intel.com> Signed-off-by: Pengfei Qu <pengfei...@

[Libva] [PATCH V4: 11/11] scaling matrix of h264 encoder on gen7/gen7.5/gen8/gen9

From: Jia Meng <jia.m...@intel.com> v1: change the title according to yakui's comments. qm is in raster scan order per va api, and fqm is in column wise raster scan order per hardware requirement. Signed-off-by: Jia Meng <jia.m...@intel.com> Signed-off-by: Pengfei Qu <pengf

[Libva] [PATCH V4: 01/11] Encoding: mbmv cost table related changes for ROI

passed, the buffer length should be enlarged. Pass the Qp parameter into VME shader Signed-off-by: Zhao Yakui <yakui.z...@intel.com> Signed-off-by: pjl <cecilia.p...@intel.com> Signed-off-by: Pengfei Qu <pengfei...@intel.com> --- src

[Libva] [PATCH V4: 02/11] Encoding: VME shader reads mbmv_cost from cost_table surface instead of constant buffer on Haswell

From: Zhao Yakui <yakui.z...@intel.com> This is to do the prepartion of enhanced features. Signed-off-by: Zhao Yakui <yakui.z...@intel.com> Signed-off-by: pjl <cecilia.p...@intel.com> Signed-off-by: Pengfei Qu <pengfei...@intel.com> --- src/shaders/vme/inter_

[Libva] [PATCH V3: 10/11] Adjust the maximum number of motion vectors for B frame on HSW+

From: Jia Meng <jia.m...@intel.com> Signed-off-by: Jia Meng <jia.m...@intel.com> Signed-off-by: Pengfei Qu <pengfei...@intel.com> --- src/gen75_vme.c | 13 +++-- src/gen8_vme.c | 15 --- src/gen9_vme.c | 17 + 3 files changed, 24 insertion

[Libva] [PATCH V3: 07/11] encoding:use the qp per every macroblock on Ivy and haswell

From: Zhao Yakui <yakui.z...@intel.com> v1: combine the patch together for Ivy and haswell use-CPU-to-construct-the-MFC-pak-command Signed-off-by: Zhao Yakui <yakui.z...@intel.com> Signed-off-by: ceciliapeng <cecilia.p...@intel.com> Signed-off-by: Pengfei Qu <pengfei..

[Libva] [PATCH V3: 03/11] encoding: Send VME instruction uses one register as the desc parameter

From: Zhao Yakui <yakui.z...@intel.com> The desc parameter of current VME send instruction is hardcode. And it can't be updated based on the input parameter. Signed-off-by: Zhao Yakui <yakui.z...@intel.com> Signed-off-by: pjl <cecilia.p...@intel.com> Signed-off-by: P

[Libva] [PATCH V3: 09/11] ROI:enable on gen8 and gen9

v1: ROI enable on gen8 and gen9 Enable GPU to construct GPU command under ROI scenario fix roi attrib config incorrectly Signed-off-by: Zhao Yakui <yakui.z...@intel.com> Signed-off-by: Pengfei Qu <pengfei...@intel.com> --- src/gen6_mfc_c

[Libva] [PATCH V3: 04/11] Encoding: Pass the qp parameter into VME shader and VME shader select the different cost table based on input Qp on Ivy

put Qp. Signed-off-by: Zhao Yakui <yakui.z...@intel.com> Signed-off-by: pjl <cecilia.p...@intel.com> Signed-off-by: Pengfei Qu <pengfei...@intel.com> --- src/gen6_mfc_common.c| 1 + src/gen7_vme.c | 155 +---

[Libva] [PATCH V3: 11/11] scaling matrix of h264 encoder on gen7/gen7.5/gen8/gen9

From: Jia Meng <jia.m...@intel.com> v1: change the title according to yakui's comments. qm is in raster scan order per va api, and fqm is in column wise raster scan order per hardware requirement. Signed-off-by: Jia Meng <jia.m...@intel.com> Signed-off-by: Pengfei Qu <pengf

[Libva] [PATCH V3: 08/11] Encoding: ROI support for CQP/CBR on Haswell/Ivy

_value = intel_qpvalue_from_qp(qp)) Qp_value_roi * ROI_area + qp_value_nonroi * area_nonroi = base_qp * total_area. Signed-off-by: ceciliapeng <cecilia.p...@intel.com> Signed-off-by: Pengfei Qu <pengfei...@intel.com> --- src/gen6_mfc_common.c | 202 +

[Libva] [PATCH V3: 01/11] Encoding: mbmv cost table related changes for ROI

passed, the buffer length should be enlarged. Pass the Qp parameter into VME shader Signed-off-by: Zhao Yakui <yakui.z...@intel.com> Signed-off-by: pjl <cecilia.p...@intel.com> Signed-off-by: Pengfei Qu <pengfei...@intel.com> --- src

[Libva] [PATCH V3: 06/11] Encoding: Add one ROI flag and ROI buffer

; Signed-off-by: pjl <cecilia.p...@intel.com> Signed-off-by: Pengfei Qu <pengfei...@intel.com> --- src/gen6_mfc_common.c | 70 +++ src/gen6_vme.h| 13 ++ src/i965_encoder.c| 7 -- src/i965_encoder.h| 1 + 4 file

[Libva] [PATCH V3: 02/11] Encoding: VME shader reads mbmv_cost from cost_table surface instead of constant buffer on Haswell

From: Zhao Yakui <yakui.z...@intel.com> This is to do the prepartion of enhanced features. Signed-off-by: Zhao Yakui <yakui.z...@intel.com> Signed-off-by: pjl <cecilia.p...@intel.com> Signed-off-by: Pengfei Qu <pengfei...@intel.com> --- src/shaders/vme/inter_

[Libva] [PATCH V3: 05/11] Encoding: Dynamically select one mechanism to construct encoding command buffer for each frame on Haswell and Gen7/Gen6

ferent mechanism on the fly instead of statically compiled mode. Signed-off-by: Zhao Yakui <yakui.z...@intel.com> Signed-off-by: pjl <cecilia.p...@intel.com> Signed-off-by: Pengfei Qu <pengfei...@intel.com> --- src/gen6_mfc.c | 12 src/gen6_mfc.h | 1 -

[Libva] [PATCH V3: 00/11]Add ROI feature on Gen7/Gen7.5/Gen8/Gen9 and scaling list features.

of motion vectors for B frame on HSW+ scaling matrix of h264 encoder on gen7/gen7.5/gen8/gen9 Pengfei Qu (1): ROI:enable on gen8 and gen9 Zhao Yakui (8): Encoding: mbmv cost table related changes for ROI Encoding: VME shader reads mbmv_cost from cost_table surface instead of constant

[Libva] [PATCH 06/12] Encoding: Add one ROI flag and ROI buffer

From: Zhao Yakui <yakui.z...@intel.com> v1: Add one flag to indicate whether ROI is supported in one encode context Allocate one ROI buffer to hold qp per mb dynamically Signed-off-by: Zhao Yakui <yakui.z...@intel.com> Signed-off-by: pjl <cecilia.p...@intel.com> Signed-

[Libva] [PATCH 10/12] Adjust the maximum number of motion vectors for B frame on HSW+

From: Jia Meng <jia.m...@intel.com> Signed-off-by: Jia Meng <jia.m...@intel.com> Signed-off-by: Pengfei Qu <pengfei...@intel.com> --- src/gen75_vme.c | 13 +++-- src/gen8_vme.c | 15 --- src/gen9_vme.c | 17 + 3 files changed, 24 insertion

[Libva] [PATCH 09/12] ROI:enable on gen8 and gen9

v1: ROI enable on gen8 and gen9 Enable GPU to construct GPU command under ROI scenario fix roi attrib config incorrectly Signed-off-by: Zhao Yakui <yakui.z...@intel.com> Signed-off-by: Pengfei Qu <pengfei...@intel.com> --- src/gen6_mfc_c

[Libva] [PATCH 08/12] Encoding: ROI support for CQP/CBR on Haswell/Ivy

_qp(qp)) Qp_value_roi * ROI_area + qp_value_nonroi * area_nonroi = base_qp * total_area. Signed-off-by: ceciliapeng <cecilia.p...@intel.com> Signed-off-by: Pengfei Qu <pengfei...@intel.com> --- src/gen6_mfc_common.c | 205 -- src/i965_drv_video.c

[Libva] [PATCH 01/12] Encoding: mbmv cost table related changes for ROI

the Qp parameter into VME shader Signed-off-by: Zhao Yakui <yakui.z...@intel.com> Signed-off-by: pjl <cecilia.p...@intel.com> Signed-off-by: Pengfei Qu <pengfei...@intel.com> --- src/gen6_mfc_common.c | 161 +++--- src/gen6_vme.h

[Libva] [PATCH 03/12] encoding: Send VME instruction uses one register as the desc parameter instead of hardcode

From: Zhao Yakui <yakui.z...@intel.com> The desc parameter of current VME send instruction is hardcode. And it can't be updated based on the input parameter. Signed-off-by: Zhao Yakui <yakui.z...@intel.com> Signed-off-by: pjl <cecilia.p...@intel.com> Signed-off-by: P

[Libva] [PATCH 05/12] Encoding: Dynamically select one mechanism to construct encoding command buffer for each frame on Haswell and Gen7/Gen6

nstead of statically compiled mode. Signed-off-by: Zhao Yakui <yakui.z...@intel.com> Signed-off-by: pjl <cecilia.p...@intel.com> Signed-off-by: Pengfei Qu <pengfei...@intel.com> --- src/gen6_mfc.c | 12 src/gen6_mfc.h | 1 - src/gen75_mfc.c| 15 +--

[Libva] [PATCH 12/12] QP difference configuration for adjacent IP and PB frames

From: Jia Meng <jia.m...@intel.com> v1: use max_qp_delta_ip/pb from va Signed-off-by: Jia Meng <jia.m...@intel.com> Signed-off-by: Pengfei Qu <pengfei...@intel.com> --- src/gen6_mfc.h| 4 src/gen6_mfc_common.c | 41 + 2

[Libva] [PATCH 11/12] scaling matrix of h264 encoder on gen7/gen7.5/gen8/gen9

From: Jia Meng <jia.m...@intel.com> v1: change the title according to yakui's comments. qm is in raster scan order per va api, and fqm is in column wise raster scan order per hardware requirement. Signed-off-by: Jia Meng <jia.m...@intel.com> Signed-off-by: Pengfei Qu <pengf

[Libva] [PATCH 04/12] Encoding: Pass the qp parameter into VME shader and VME shader select the different cost table based on input Qp on Ivy

Yakui <yakui.z...@intel.com> Signed-off-by: pjl <cecilia.p...@intel.com> Signed-off-by: Pengfei Qu <pengfei...@intel.com> --- src/gen7_vme.c | 156 +-- src/shaders/vme/inter_bframe_ivb.asm | 13 ++- src/shaders/vme/inter_bframe_i

[Libva] [PATCH 07/12] encoding:use the qp per every macroblock on Ivy and haswell

From: Zhao Yakui <yakui.z...@intel.com> v1: combine the patch together for Ivy and haswell use-CPU-to-construct-the-MFC-pak-command Signed-off-by: Zhao Yakui <yakui.z...@intel.com> Signed-off-by: ceciliapeng <cecilia.p...@intel.com> Signed-off-by: Pengfei Qu <pengfei..

[Libva] [PATCH 02/12] Encoding: VME shader reads mbmv_cost from cost_table surface instead of constant buffer on Haswell

From: Zhao Yakui <yakui.z...@intel.com> This is to do the prepartion of enhanced features. Signed-off-by: Zhao Yakui <yakui.z...@intel.com> Signed-off-by: pjl <cecilia.p...@intel.com> Signed-off-by: Pengfei Qu <pengfei...@intel.com> --- src/shaders/vme/inter_

[Libva] [PATCH 00/12] Add ROI feature on Gen7/Gen7.5/Gen8/Gen9 and scaling list features.

+ scaling matrix of h264 encoder on gen7/gen7.5/gen8/gen9 QP difference configuration for adjacent IP and PB frames Pengfei Qu (1): ROI:enable on gen8 and gen9 Zhao Yakui (8): Encoding: mbmv cost table related changes for ROI Encoding: VME shader reads mbmv_cost from cost_table surface instead

[Libva] [PATCH 11/13] Adjust the maximum number of motion vectors for B frame on HSW+

From: Jia Meng <jia.m...@intel.com> Signed-off-by: Jia Meng <jia.m...@intel.com> Signed-off-by: Pengfei Qu <pengfei...@intel.com> --- src/gen75_vme.c | 13 +++-- src/gen8_vme.c | 15 --- src/gen9_vme.c | 17 + 3 files changed, 24 insertion

[Libva] [PATCH 13/13] QP difference configuration for adjacent IP and PB frames

From: Jia Meng <jia.m...@intel.com> v1: use max_qp_delta_ip/pb from va Signed-off-by: Jia Meng <jia.m...@intel.com> Signed-off-by: Pengfei Qu <pengfei...@intel.com> --- src/gen6_mfc.h| 4 src/gen6_mfc_common.c | 41 + 2

[Libva] [PATCH 12/13] scaling matrix of h264 encoder on gen7/gen7.5/gen8/gen9

From: Jia Meng <jia.m...@intel.com> v1: change the title according to yakui's comments. qm is in raster scan order per va api, and fqm is in column wise raster scan order per hardware requirement. Signed-off-by: Jia Meng <jia.m...@intel.com> Signed-off-by: Pengfei Qu <pengf

[Libva] [PATCH 08/13] Encoding: ROI support for CQP/CBR on Haswell/Ivy

_qp(qp)) Qp_value_roi * ROI_area + qp_value_nonroi * area_nonroi = base_qp * total_area. Signed-off-by: ceciliapeng <cecilia.p...@intel.com> Signed-off-by: Pengfei Qu <pengfei...@intel.com> --- src/gen6_mfc_common.c | 205 -- src/i965_drv_video.c

[Libva] [PATCH 06/13] Encoding: Add one ROI flag and ROI buffer

From: Zhao Yakui <yakui.z...@intel.com> v1: Add one flag to indicate whether ROI is supported in one encode context Allocate one ROI buffer to hold qp per mb dynamically Signed-off-by: Zhao Yakui <yakui.z...@intel.com> Signed-off-by: pjl <cecilia.p...@intel.com> Signed-

[Libva] [PATCH 09/13] ROI:enable on gen8 and gen9

v1: ROI enable on gen8 and gen9 Enable GPU to construct GPU command under ROI scenario fix roi attrib config incorrectly Signed-off-by: Zhao Yakui <yakui.z...@intel.com> Signed-off-by: Pengfei Qu <pengfei...@intel.com> --- src/gen6_mfc_common.c| 20 ++-- sr

[Libva] [PATCH 04/13] Encoding: Pass the qp parameter into VME shader and VME shader select the different cost table based on input Qp on Ivy

Yakui <yakui.z...@intel.com> Signed-off-by: pjl <cecilia.p...@intel.com> Signed-off-by: Pengfei Qu <pengfei...@intel.com> --- src/gen7_vme.c | 156 +-- src/shaders/vme/inter_bframe_ivb.asm | 13 ++- src/shaders/vme/inter_bframe_i

[Libva] [PATCH 07/13] encoding:use the qp per every macroblock on Ivy and haswell

From: Zhao Yakui <yakui.z...@intel.com> v1: combine the patch together for Ivy and haswell use-CPU-to-construct-the-MFC-pak-command Signed-off-by: Zhao Yakui <yakui.z...@intel.com> Signed-off-by: ceciliapeng <cecilia.p...@intel.com> Signed-off-by: Pengfei Qu <pengfei..

[Libva] [PATCH 02/13] Encoding: VME shader reads mbmv_cost from cost_table surface instead of constant buffer on Haswell

From: Zhao Yakui <yakui.z...@intel.com> This is to do the prepartion of enhanced features. Signed-off-by: Zhao Yakui <yakui.z...@intel.com> Signed-off-by: pjl <cecilia.p...@intel.com> Signed-off-by: Pengfei Qu <pengfei...@intel.com> --- src/shaders/vme/inter_

[Libva] [PATCH 03/13] encoding: Send VME instruction uses one register as the desc parameter instead of hardcode

From: Zhao Yakui <yakui.z...@intel.com> The desc parameter of current VME send instruction is hardcode. And it can't be updated based on the input parameter. Signed-off-by: Zhao Yakui <yakui.z...@intel.com> Signed-off-by: pjl <cecilia.p...@intel.com> Signed-off-by: P

[Libva] [PATCH 00/13] Add ROI feature on Gen7/Gen7.5/Gen8/Gen9 and scaling list features.

this add ROI feature on Gen7/Gen7.5/Gen8/Gen9 and scaling list features. Jia Meng (3): Adjust the maximum number of motion vectors for B frame on HSW+ scaling matrix of h264 encoder on gen8/gen9 QP difference configuration for adjacent IP and PB frames Pengfei Qu (2): ROI:enable on gen8

[Libva] [PATCH 01/13] Encoding: mbmv cost table related changes for ROI

the Qp parameter into VME shader Signed-off-by: Zhao Yakui <yakui.z...@intel.com> Signed-off-by: pjl <cecilia.p...@intel.com> Signed-off-by: Pengfei Qu <pengfei...@intel.com> --- src/gen6_mfc_common.c | 161 +++--- src/gen6_vme.h

[Libva] [PATCH 3/3] add ip/pb qp diff configuration

From: Jia Meng <jia.m...@intel.com> v1: add the interface for max QP delta between frames, such as IP frame and PB frame. is is used in CBR mode. v2: change the member name to max_qp_delta_ip/pb Signed-off-by: Jia Meng <jia.m...@intel.com> Signed-off-by: Pengfei Qu <pengf

[Libva] [PATCH 07/14] Encoding: Add one ROI flag and ROI buffer

From: Zhao Yakui <yakui.z...@intel.com> v1: Add one flag to indicate whether ROI is supported in one encode context Allocate one ROI buffer to hold qp per mb dynamically Signed-off-by: Zhao Yakui <yakui.z...@intel.com> Signed-off-by: pjl <ceciliap...@intel.com> Signed-off-by: P

[Libva] [PATCH 13/14] scaling matrix of h264 encoder on gen8/gen9

From: Jia Meng <jia.m...@intel.com> qm is in raster scan order per va api, and fqm is in column wise raster scan order per hardware requirement. Signed-off-by: Jia Meng <jia.m...@intel.com> Signed-off-by: Pengfei Qu <pengfei...@intel.com> --- src/gen6_mfc.c | 12 -- src

[Libva] [PATCH 04/14] encoding: Send VME instruction uses one register as the desc parameter instead of hardcode

From: Zhao Yakui <yakui.z...@intel.com> The desc parameter of current VME send instruction is hardcode. And it can't be updated based on the input parameter. Signed-off-by: Zhao Yakui <yakui.z...@intel.com> Signed-off-by: pjl <ceciliap...@intel.com> Signed-off-by: P

[Libva] [PATCH 14/14] QP difference configuration for adjacent IP and PB frames

From: Jia Meng <jia.m...@intel.com> Signed-off-by: Jia Meng <jia.m...@intel.com> Signed-off-by: Pengfei Qu <pengfei...@intel.com> --- src/gen6_mfc.h| 4 src/gen6_mfc_common.c | 41 + 2 files changed, 33 insertions(+), 12

[Libva] [PATCH 09/14] Encoding: ROI support for CQP/CBR on Haswell/Ivy

_qp(qp)) Qp_value_roi * ROI_area + qp_value_nonroi * area_nonroi = base_qp * total_area. Signed-off-by: ceciliapeng <cecilia.p...@intel.com> Signed-off-by: Pengfei Qu <pengfei...@intel.com> --- src/gen6_mfc_common.c | 205 -- src/i965_drv_video.c

[Libva] [PATCH 12/14] Adjust the maximum number of motion vectors for B frame on HSW+

From: Jia Meng <jia.m...@intel.com> Signed-off-by: Jia Meng <jia.m...@intel.com> Signed-off-by: Pengfei Qu <pengfei...@intel.com> --- src/gen75_vme.c | 13 +++-- src/gen8_vme.c | 15 --- src/gen9_vme.c | 17 + 3 files changed, 24 insertion

[Libva] [PATCH 05/14] Encoding: Pass the qp parameter into VME shader and VME shader select the different cost table based on input Qp on Ivy

Yakui <yakui.zh...@intel.com> Signed-off-by: pjl <ceciliap...@intel.com> Signed-off-by: Pengfei Qu <pengfei...@intel.com> --- src/gen7_vme.c | 156 +-- src/shaders/vme/inter_bframe_ivb.asm | 13 ++- src/shaders/vme/inter_bframe_i

[Libva] [PATCH 10/14] ROI:enable on gen8 and gen9

v1: ROI enable on gen8 and gen9 Enable GPU to construct GPU command under ROI scenario Signed-off-by: Zhao Yakui <yakui.z...@intel.com> Signed-off-by: Pengfei Qu <pengfei...@intel.com> --- src/gen6_mfc_common.c| 20 ++-- src/gen8_mfc.c | 55 +++

[Libva] [PATCH 03/14] Encoding: VME shader reads mbmv_cost from cost_table surface instead of constant buffer on Haswell

From: Zhao Yakui <yakui.z...@intel.com> This is to do the prepartion of enhanced features. Signed-off-by: Zhao Yakui <yakui.z...@intel.com> Signed-off-by: pjl <ceciliap...@intel.com> Signed-off-by: Pengfei Qu <pengfei...@intel.com> --- src/gen75_vme.c

[Libva] [PATCH 08/14] encoding:use the qp per every macroblock on Ivy and haswell

From: Zhao Yakui <yakui.z...@intel.com> v1: combine the patch together for Ivy and haswell use-CPU-to-construct-the-MFC-pak-command Signed-off-by: Zhao Yakui <yakui.z...@intel.com> Signed-off-by: ceciliapeng <cecilia.p...@intel.com> Signed-off-by: Pengfei Qu <pengfei..

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