On Tue, 2014-03-04 at 01:32 -0700, Zhao, Yakui wrote:
From: Zhao Yakui yakui.z...@intel.com
This is the patch set that tries to seperate the BDW rendering/VPP with the
previous
platform. Although some codes are duplicated, it has the following advantages:
1. It is easy to add
On Tue, 2014-03-04 at 01:32 -0700, Zhao, Yakui wrote:
From: Zhao Yakui yakui.z...@intel.com
This is the patch set that tries to seperate the BDW rendering/VPP with the
previous
platform. Although some codes are duplicated, it has the following advantages:
1. It is easy to add
Signed-off-by: Zhao Yakui yakui.z...@intel.com
---
src/i965_drv_video.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/src/i965_drv_video.c b/src/i965_drv_video.c
index 14a0926..253e06e 100755
--- a/src/i965_drv_video.c
+++ b/src/i965_drv_video.c
@@ -3210,6 +3210,16 @@ VAStatus
Signed-off-by: Zhao Yakui yakui.z...@intel.com
---
src/gen8_post_processing.c | 2 ++
src/i965_post_processing.c | 11 +--
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/src/gen8_post_processing.c b/src/gen8_post_processing.c
index f34392c..8207e02 100644
--- a/src
Signed-off-by: Zhao Yakui yakui.z...@intel.com
---
src/i965_drv_video.c | 26 +-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git a/src/i965_drv_video.c b/src/i965_drv_video.c
index 0453c04..f306d91 100755
--- a/src/i965_drv_video.c
+++ b/src/i965_drv_video.c
Signed-off-by: Zhao Yakui yakui.z...@intel.com
---
src/i965_drv_video.c | 12
1 file changed, 12 insertions(+)
diff --git a/src/i965_drv_video.c b/src/i965_drv_video.c
index f306d91..14a0926 100755
--- a/src/i965_drv_video.c
+++ b/src/i965_drv_video.c
@@ -4691,6 +4691,12
Hi, Halley
Thanks for your patch.
After adding the patch, it is possible that the upper-application can
pass the specific parameters when creating the surface. I agree with your
point.
But it seems that one thing is missing:
For the non-tiling scenario: it is
On Sun, 2014-03-16 at 19:10 -0600, Zhao, Yakui wrote:
Hi, Halley
Thanks for your patch.
After adding the patch, it is possible that the upper-application can
pass the specific parameters when creating the surface. I agree with your
point.
But it seems that one thing
On Sun, 2014-03-16 at 23:50 -0600, Xiang, Haihao wrote:
It would be better to add a pre-defined fourcc code for YV16 in va.h
Thanks for your review.
OK. I can send a patch about YV16 fourcc code for libva.
Signed-off-by: Zhao Yakui yakui.z...@intel.com
---
src/i965_drv_video.c | 26
Reviewed-by: Wind Yuan feng.y...@intel.com
Tested-by: Wind Yuan feng.y...@intel.com
Signed-off-by: Zhao Yakui yakui.z...@intel.com
---
src/i965_drv_video.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/src/i965_drv_video.c b/src/i965_drv_video.c
index 14a0926..253e06e 100755
[mailto:libva-boun...@lists.freedesktop.org] On Behalf Of Zhao
Yakui
Sent: Monday, March 17, 2014 5:08 PM
To: libva@lists.freedesktop.org
Subject: [Libva] [PATCH Libva-intel-driver 4/4] Add the csc conversion from
YV16
to NV12
V1-V2: Follow Zhiwen's comment to add the missing code when
Thank Gwenole for finding this typo error which is caused by
the commit 2b5fad11a5c12d3c6ffbef15c02449a3b4e90b98.
Signed-off-by: Zhao Yakui yakui.z...@intel.com
---
src/gen8_post_processing.c | 2 +-
src/i965_post_processing.c | 8
2 files changed, 5 insertions(+), 5 deletions(-)
diff
On Tue, 2014-03-18 at 02:35 -0600, Zhao, Yakui wrote:
Thank Gwenole for finding this typo error which is caused by
the commit 2b5fad11a5c12d3c6ffbef15c02449a3b4e90b98.
this will be pushed.
thanks.
Yakui
Signed-off-by: Zhao Yakui yakui.z...@intel.com
---
src/gen8_post_processing.c | 2
On Mon, 2014-03-17 at 00:09 -0600, Zhao, Halley wrote:
Thanks Yakui。
LGTM. this will be pushed.
thanks.
Yakui
-Original Message-
From: Zhao, Yakui
Sent: Monday, March 17, 2014 10:25 AM
To: Zhao, Halley
Cc: libva@lists.freedesktop.org
Subject: Re: [Libva] [PATCH 1/2] va
On Tue, 2014-03-18 at 23:01 -0600, Gwenole Beauchesne wrote:
2014-03-18 9:35 GMT+01:00 Zhao Yakui yakui.z...@intel.com:
Thank Gwenole for finding this typo error which is caused by
the commit 2b5fad11a5c12d3c6ffbef15c02449a3b4e90b98.
OK, but please also schedule another patch where you
On Wed, 2014-03-19 at 02:46 -0600, Zhao, Halley wrote:
Are you ok with this patch?
Hi, Halley
Thanks for the patch. The env is added to control whether the
assert(XXX) is enabled. This is still an improvement.
It seems that Gwenole's suggestion is to remove the corresponding
assert
This is helpful to avoid the typo error when using VA_FOURCC(A, B, C, D).
Signed-off-by: Zhao Yakui yakui.z...@intel.com
---
src/gen75_picture_process.c | 6 +-
src/gen75_vpp_gpe.c | 2 +-
src/gen8_post_processing.c | 42 -
src/i965_post_processing.c | 204
This is the patch set that try to use the VA_FOURCC_ABCD constant to replace
the VA_FOURCC(A,B,C,D). There is no function change. But it is helpful
to avoid the typo error of VA_FOURCC(A,B,C,D).
Zhao Yakui (4):
[Patch 01/4] Use the VA_FOURCC_ to replace the VA_FOURCC(X,X,X,X
This is helpful to avoid the typo error when using VA_FOURCC(A, B, C, D).
Signed-off-by: Zhao Yakui yakui.z...@intel.com
--
src/gen75_vpp_vebox.c | 83 --
1 file changed, 41 insertions(+), 42 deletions(-)
---
src/gen75_vpp_vebox.c | 83
On Fri, 2014-03-21 at 01:15 -0600, Xiang, Haihao wrote:
On Fri, 2014-03-21 at 14:31 +0800, zhiwen...@intel.com wrote:
From: Alex wu zhiwen...@intel.com
---
src/i965_drv_video.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/src/i965_drv_video.c
On Thu, 2014-03-20 at 00:24 -0600, Zhao, Yakui wrote:
This is the patch set that try to use the VA_FOURCC_ABCD constant to replace
the VA_FOURCC(A,B,C,D). There is no function change. But it is helpful
to avoid the typo error of VA_FOURCC(A,B,C,D).
Zhao Yakui (4):
[Patch 01/4] Use
On Sun, 2014-03-23 at 19:54 -0600, Wu, Zhiwen wrote:
From: Alex wu zhiwen...@intel.com
Changes to V1:
1. Rebase on staging branch.
2. Add 422H support for pp.
3. Reword the commit title.
This patch is OK to me except the missing piece in file of
gen8_post_processing.c.
if (fourcc ==
On Sun, 2014-03-23 at 21:28 -0600, Xiang, Haihao wrote:
No. Please rebase it against the latest branch.
s/VA_FOURCC(x, x, x, x)/VA_FOURCC_
Thanks for the info.
OK. I already help to handle it manually before pushing it.
Thanks.
Yakui
Thanks
Haihao
On Sun, 2014-03-23 at
On Sun, 2014-03-23 at 20:49 -0600, Zhao, Yakui wrote:
The commit 7ac4263ff2dae5c877b92356d04df4ccfe10d7c9 updates
the shader binary more than it required. So it is removed.
This will be pushed.
Thanks.
Yakui
Signed-off-by: Zhao Yakui yakui.z...@intel.com
---
src/shaders/vme
On Thu, 2014-03-27 at 10:46 -0600, Nik Orlov wrote:
Hello! Thanks!
As I see, libva can use X11 or direct DRM, and it can`t use DRM when system
has running X11. Am I right?
I will have research (google) about relations between dri and drm.
Hi, Nik
What Matt said is right. The libva
On Mon, 2014-04-14 at 02:17 -0600, Zhong Li wrote:
Signed-off-by: Zhong Li zhong...@intel.com
The Imageformat for JPEG should also be added.
Thanks.
Yakui
---
src/i965_drv_video.c |6 ++
1 file changed, 6 insertions(+)
diff --git a/src/i965_drv_video.c b/src/i965_drv_video.c
On Mon, 2014-04-14 at 20:20 -0600, Xiang, Haihao wrote:
From: Xiang, Haihao haihao.xi...@intel.com
Otherwise it might result in buffer overflow.
Good catch.
This looks good to me.
Reviewed-by: Zhao Yakui yakui.z...@intel.com
Thanks.
Yakui
Signed-off-by: Xiang, Haihao haihao.xi
On Tue, 2014-04-15 at 20:48 -0600, lizhong wrote:
Yes, IMC3 is required for JPEG decoding driver. I added IMC3 to follow
decoding driver.
Agree. IMC3 is required for JPEG decoding and the driver will allocate
the tiling surface for IMC3. But the I420 is handled as non-tiling by
the driver. So
On Mon, 2014-04-14 at 20:20 -0600, Xiang, Haihao wrote:
From: Xiang, Haihao haihao.xi...@intel.com
Otherwise it might result in buffer overflow.
LGTM.
Pushed.
Thanks.
Signed-off-by: Xiang, Haihao haihao.xi...@intel.com
---
src/i965_drv_video.c | 2 +-
1 file changed, 1 insertion(+),
On Wed, 2014-04-16 at 06:23 -0600, Gwenole Beauchesne wrote:
2014-04-15 17:48 GMT-07:00 Xiang, Haihao haihao.xi...@intel.com:
On Tue, 2014-04-15 at 07:27 -0700, Gwenole Beauchesne wrote:
Hi,
2014-04-14 1:17 GMT-07:00 Zhong Li zhong...@intel.com:
Signed-off-by: Zhong Li
Currently zero is written to alpha channel when doing the conversion
from NV12 to RGBA(BGRA), which affects the following the rendering operation.
Signed-off-by: Zhao Yakui yakui.z...@intel.com
---
src/gen8_post_processing.c |1 +
src/i965_post_processing.c |1 +
src
for NV12 */
+v_dst = (unsigned char *)((unsigned char *)surface_p +
surface_image.offsets[2]);
This make sense.
Of course the left (unsigned char *) outside of the parentheses can be
removed. Anyway this is OK to me.
reviewed-by: Zhao Yakui yakui.z...@intel.com
/* Y plane
On Sun, 2014-05-04 at 23:00 -0600, Xiang, Haihao wrote:
From: Xiang, Haihao haihao.xi...@intel.com
Make sense.
Reviewed-by: Zhao Yakui yakui.z...@intel.com
Signed-off-by: Xiang, Haihao haihao.xi...@intel.com
---
src/va_backend_compat.h | 6 ++
1 file changed, 6 insertions(+)
diff
to bypass the vaPutSurface.
At the same time it also needs to add the function of waiting for the
completion of decoding.
Thanks
Haihao
From: Zhao Yakui yakui.z...@intel.com
Signed-off-by: Zhao Yakui yakui.z...@intel.com
---
src/i965_drv_video.h | 3 +++
src/i965_output_dri.c | 4
On Wed, 2014-05-07 at 12:32 -0600, Torbjorn Tyridal wrote:
Hi,
Is it possible to select which reference frames to consider when
encoding a frame with libva (Intel, haswell)?
The upper user-space application will pass the reference picture list0/1
for H264 encoding and then the libva
.
(This is to assure that the previous decoding is finished).
Thanks.
Yakui
Thanks
-Austin
-Original Message-
From: Libva [mailto:libva-boun...@lists.freedesktop.org] On Behalf Of Zhao
Yakui
Sent: Tuesday, May 06, 2014 12:50 PM
To: Xu, Guangxin
Cc: z...@freedesktop.org; libva
the vaSyncSurface for the dummy vaPutSurface.
Thanks.
Yakui
Thanks
-Austin
-Original Message-
From: Libva [mailto:libva-boun...@lists.freedesktop.org] On Behalf Of Zhao
Yakui
Sent: Thursday, May 08, 2014 4:10 PM
To: Yuan, Shengquan
Cc: libva@lists.freedesktop.org
Subject: Re: [Libva
On Fri, 2014-05-09 at 08:34 -0600, Gwenole Beauchesne wrote:
Drop the optimization whereby surfaces that are no longer marked as
reference and that were already displayed are to be destroyed. This
is wrong mainly for two reasons:
1. The surface was displayed... once but it may still be
On Sat, 2014-05-10 at 00:03 -0600, Gwenole Beauchesne wrote:
Hi,
This patch series fixes and optimizes support for grayscale streams (Patch5).
Patches 2 to 4 are colateral preparatory work for fixing VA config
queries and creation.
Hi, Gwenole
Are you testing it by using
On Sat, 2014-05-10 at 00:03 -0600, Gwenole Beauchesne wrote:
Optimize support for grayscale surfaces in two aspects: (i) space
by only allocating the luma component ; (ii) speed by avoiding
initialization of the (now inexistent) chroma planes.
Keep backward compatibility with older codec
On Fri, 2014-05-09 at 03:06 -0600, Yuan, Feng wrote:
Hi,
I have a scheme where the decoder ack's received frames - With this
information I could resync without an IDR by carefully selecting the
reference frame(s).
Will you please describe your idea in detail?
long term references
with.
Regards,
Gwenole.
-Original Message-
From: Libva [mailto:libva-boun...@lists.freedesktop.org] On Behalf Of Zhao
Yakui
Sent: Tuesday, May 6, 2014 12:36 PM
To: Xiang, Haihao
Cc: z...@freedesktop.org; libva@lists.freedesktop.org
Subject: Re: [Libva] [PATCH Libva-intel-driver
Of Gwenole
Beauchesne
Sent: Friday, May 9, 2014 3:38 AM
To: Zhao, Yakui
Cc: libva@lists.freedesktop.org
Subject: Re: [Libva] [PATCH Libva-intel-driver] Add one option of bypassing
rendering function to test decoding
Hi,
2014-05-08 10:24 GMT+02:00 Zhao Yakui yakui.z...@intel.com:
On Thu
On Sun, 2014-05-11 at 22:26 -0600, Gwenole Beauchesne wrote:
Hi,
2014-05-12 3:21 GMT+02:00 Zhao Yakui yakui.z...@intel.com:
On Sat, 2014-05-10 at 00:03 -0600, Gwenole Beauchesne wrote:
Optimize support for grayscale surfaces in two aspects: (i) space
by only allocating the luma component
On Sun, 2014-05-11 at 22:41 -0600, Gwenole Beauchesne wrote:
Hi,
2014-05-12 3:34 GMT+02:00 Zhao Yakui yakui.z...@intel.com:
On Fri, 2014-05-09 at 03:06 -0600, Yuan, Feng wrote:
Hi,
I have a scheme where the decoder ack's received frames - With this
information I could resync
On Tue, 2014-05-13 at 03:20 -0600, Zhong Li wrote:
Support VAEncFEIMVBufferTypeIntel and VAEntrypointEncFEIIntel
Signed-off-by: Zhong Li zhong...@intel.com
---
src/i965_drv_video.c | 37 -
src/i965_drv_video.h |1 +
2 files changed, 25
On Tue, 2014-05-13 at 03:20 -0600, Zhong Li wrote:
Get motion vectors of vme output by FEI interface.
Set mv to be 0x8000 when intra MB.
Signed-off-by: Zhong Li zhong...@intel.com
---
src/gen6_mfc.c | 73
src/gen6_vme.h |2
On 05/14/2014 08:48 AM, Zhao, Yakui wrote:
On Tue, 2014-05-13 at 03:20 -0600, Zhong Li wrote:
Support VAEncFEIMVBufferTypeIntel and VAEntrypointEncFEIIntel
Signed-off-by: Zhong Li zhong...@intel.com
---
src/i965_drv_video.c | 37 -
src
On Sun, 2014-05-11 at 23:34 -0600, Gwenole Beauchesne wrote:
2014-05-12 7:29 GMT+02:00 Zhao, Yakui yakui.z...@intel.com:
On Sun, 2014-05-11 at 22:41 -0600, Gwenole Beauchesne wrote:
Hi,
2014-05-12 3:34 GMT+02:00 Zhao Yakui yakui.z...@intel.com:
On Fri, 2014-05-09 at 03:06 -0600, Yuan
On Wed, 2014-05-14 at 01:47 -0600, Gwenole Beauchesne wrote:
Simplify the construction of the MI_FLUSH_DW command stream. Use ring
buffer generic variants of BEGIN, OUT, ADVANCE batch functions.
Hi, Gwenole
Thanks for your patch.
But I don't think that we need factor out of
On Wed, 2014-05-14 at 01:47 -0600, Gwenole Beauchesne wrote:
The MI_FLUSH_DW command contains 5 dwords on Broadwell, i.e. one extra
dword for the high order bits of the Address field.
Thanks for your patch.
What is wrong if this is applied?
The 4 dwords are still ok to Broadwell. And the
On Wed, 2014-05-14 at 10:27 +0200, Gwenole Beauchesne wrote:
Hi,
2014-05-14 10:10 GMT+02:00 Zhao, Yakui yakui.z...@intel.com:
On Wed, 2014-05-14 at 01:47 -0600, Gwenole Beauchesne wrote:
The MI_FLUSH_DW command contains 5 dwords on Broadwell, i.e. one extra
dword for the high order bits
On Wed, 2014-05-14 at 07:13 -0600, Gwenole Beauchesne wrote:
Allow vaDeriveImage() to work with grayscale surfaces by only exposing
the luma component.
This is not necessary as the DeriveImage already supports the Y800
fourcc.
Signed-off-by: Gwenole Beauchesne gwenole.beauche...@intel.com
On Wed, 2014-05-14 at 07:13 -0600, Gwenole Beauchesne wrote:
Optimize support for grayscale surfaces in two aspects: (i) space
by only allocating the luminance component ; (ii) speed by avoiding
initialization of the (now inexistent) chrominance planes.
Keep backward compatibility with older
On Wed, 2014-05-14 at 03:50 -0600, Sreerenj wrote:
On 14.05.2014 10:51, Xiang, Haihao wrote:
On Mon, 2014-05-12 at 07:34 +0200, Gwenole Beauchesne wrote:
2014-05-12 7:29 GMT+02:00 Zhao, Yakui yakui.z...@intel.com:
On Sun, 2014-05-11 at 22:41 -0600, Gwenole Beauchesne wrote:
Hi,
2014
On Wed, 2014-05-14 at 22:14 -0600, Gwenole Beauchesne wrote:
2014-05-15 2:35 GMT+02:00 Zhao, Yakui yakui.z...@intel.com:
On Wed, 2014-05-14 at 07:13 -0600, Gwenole Beauchesne wrote:
Allow vaDeriveImage() to work with grayscale surfaces by only exposing
the luma component
On Wed, 2014-05-14 at 22:28 -0600, Gwenole Beauchesne wrote:
Hi,
2014-05-15 3:34 GMT+02:00 Zhao, Yakui yakui.z...@intel.com:
On Wed, 2014-05-14 at 07:13 -0600, Gwenole Beauchesne wrote:
Optimize support for grayscale surfaces in two aspects: (i) space
by only allocating the luminance
On Thu, 2014-05-15 at 00:05 -0600, Gwenole Beauchesne wrote:
Hi,
2014-05-15 7:24 GMT+02:00 Zhao, Yakui yakui.z...@intel.com:
On Wed, 2014-05-14 at 22:28 -0600, Gwenole Beauchesne wrote:
Hi,
2014-05-15 3:34 GMT+02:00 Zhao, Yakui yakui.z...@intel.com:
On Wed, 2014-05-14 at 07:13 -0600
From: Zhao, Yakui yakui.z...@intel.com
When the packed header data from user is inserted into the coded clip, it uses
the hacked code to check the number of HW skip emulation bytes. This is wrong.
So fix it.
Of course if the packed header data is generated by the driver, it is
unnecessary
From: Zhao, Yakui yakui.z...@intel.com
Under some encoding scenario, the user-space app hopes that the driver can
insert the passed packed rawdata into the coded clip. But the insertion of
packed rawdata is related with the slice. So some data structures are added
so that it can store how
From: Zhao Yakui yakui.z...@intel.com
Under some encoding scenario the user-space app hopes that the driver
can insert passed packed header rawdata/slice data into the coded clip.
This is the patch set that adds the support of inserting the packed header
rawdata/slice data from the user
From: Zhao, Yakui yakui.z...@intel.com
Under some encoding scenario, the user hopes to generate the packed slice
header data by themself and then the driver can insert the passed slice
header packed data into the coded clip. And it follows the below points:
1.The VA_ENC_PACKED_HEADER_SLICE flag
From: Zhao, Yakui yakui.z...@intel.com
After adding the support of inserting the packed rawdata, more group of packed
header data
can be passed. In order to insert the packed rawdata correctly, the packed
header type/
data should be paired.
Signed-off-by: Zhao Yakui yakui.z...@intel.com
From: Zhao, Yakui yakui.z...@intel.com
Otherwise the slice qp is inconsistent and the encoding is incorrect.
Signed-off-by: Zhao Yakui yakui.z...@intel.com
---
src/gen6_mfc.c | 6 --
src/gen75_mfc.c | 6 --
src/gen8_mfc.c | 6 --
3 files changed, 12 insertions(+), 6 deletions
From: Zhao, Yakui yakui.z...@intel.com
Under some encoding scenario, the user-space application hopes that the driver
can insert the passed packed rawdata into the coded clip. This is to allow the
insertion of packed rawdata passed from user. As the position of packed rawdata
is related
On Wed, 2014-05-21 at 00:26 -0600, Gwenole Beauchesne wrote:
Hi Yakui,
Thanks for working on this. Additional comments.
Thanks for your comment.
2014-05-21 7:51 GMT+02:00 Zhao, Yakui yakui.z...@intel.com:
When the packed header data from user is inserted into the coded clip, it
uses
On Wed, 2014-05-21 at 00:57 -0600, Zhao, Yakui wrote:
On Wed, 2014-05-21 at 00:26 -0600, Gwenole Beauchesne wrote:
Hi Yakui,
Thanks for working on this. Additional comments.
Thanks for your comment.
2014-05-21 7:51 GMT+02:00 Zhao, Yakui yakui.z...@intel.com:
When the packed
From: Zhao Yakui yakui.z...@intel.com
Under some encoding scenario the user-space app hopes that the driver
can insert passed packed header rawdata/slice data into the coded clip.
This is the patch set that adds the support of inserting the packed header
rawdata/slice data from the user
From: Zhao, Yakui yakui.z...@intel.com
When the packed header data from user is inserted into the coded clip, it uses
the hacked code to check the number of HW skip emulation bytes. This is wrong.
So fix it.
Of course if the packed header data is generated by the driver, it is
unnecessary
From: Zhao, Yakui yakui.z...@intel.com
Under some encoding scenario, the user-space application hopes that the driver
can insert the passed packed rawdata into the coded clip. But the insertion of
packed rawdata is related with the slice. So some data structures are added so
that it can store how
From: Zhao, Yakui yakui.z...@intel.com
Under some encoding scenario, the user-space application hopes that the driver
can insert the passed packed rawdata into the coded clip. This is to allow the
insertion of packed rawdata passed from user. As the position of packed rawdata
is related
From: Zhao, Yakui yakui.z...@intel.com
After adding the support of inserting the packed rawdata, more group of packed
header data
can be passed. In order to insert the packed rawdata correctly, the packed
header type/
data should be paired.
Signed-off-by: Zhao Yakui yakui.z...@intel.com
From: Zhao, Yakui yakui.z...@intel.com
Under some encoding scenario, the user hopes to generate the packed slice
header data by themself and then the driver can insert the passed slice
header packed data into the coded clip.
1.The VA_ENC_PACKED_HEADER_SLICE flag is exported and it is treated
From: Zhao, Yakui yakui.z...@intel.com
Otherwise the slice qp is inconsistent and the encoding is incorrect.
Signed-off-by: Zhao Yakui yakui.z...@intel.com
---
src/gen6_mfc.c | 6 --
src/gen75_mfc.c | 6 --
src/gen8_mfc.c | 6 --
3 files changed, 12 insertions(+), 6 deletions
On Wed, 2014-05-21 at 18:51 -0600, Zhao, Yakui wrote:
From: Zhao Yakui yakui.z...@intel.com
Under some encoding scenario the user-space app hopes that the driver
can insert passed packed header rawdata/slice data into the coded clip.
This is the patch set that adds the support of inserting
/show_bug.cgi?id=77041
Signed-off-by: Xiang, Haihao haihao.xi...@intel.com
Looks good to me.
Add: Reviewed-by: Zhao, Yakui yakui.z...@intel.com
Thanks.
Yakui
---
src/gen7_mfd.c | 29 +++--
1 file changed, 27 insertions(+), 2 deletions(-)
diff --git a/src/gen7_mfd.c
On Mon, 2014-05-26 at 18:45 -0600, Xiang, Haihao wrote:
On Mon, 2014-05-26 at 16:25 +0800, Zhao, Yakui wrote:
On Sun, 2014-05-25 at 22:40 -0600, Xiang, Haihao wrote:
From: Xiang, Haihao haihao.xi...@intel.com
and hold all supported fourcc in an array
Signed-off-by: Xiang
On Mon, 2014-05-26 at 22:08 -0600, Xiang, Haihao wrote:
From: Xiang, Haihao haihao.xi...@intel.com
and hold all supported fourcc in an array
v2: bpp[] in bit and fix the vertical factor for 411P (Yakui)
Signed-off-by: Xiang, Haihao haihao.xi...@intel.com
---
src/i965_drv_video.c | 193
-by: Zhao, Yakui yakui.z...@intel.com
Thanks.
Yakui
Signed-off-by: Xiang, Haihao haihao.xi...@intel.com
---
src/gen8_post_processing.c | 30 +++---
src/i965_post_processing.c | 33 ++---
2 files changed, 33 insertions(+), 30 deletions
On Tue, 2014-05-27 at 05:18 -0600, sreerenj.balachand...@intel.com
wrote:
From: Sreerenj Balachandran sreerenj.balachand...@intel.com
This patch looks good to me.
This will be pushed.
Thanks.
Yakui
---
src/gen6_mfc_common.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
On Tue, 2014-05-27 at 02:59 -0600, Zhao, Halley wrote:
From: Zhao, Halley halley.z...@intel.com
VA_INTEL_DEBUG_ASSERT decides assert() is enabled or not
VA_INTEL_DEBUG_BENCH decides skip putsurface or not
As a whole, this patch looks good to me except one small concern.
---
On Tue, 2014-05-27 at 19:49 -0600, Xiang, Haihao wrote:
On Wed, 2014-05-28 at 08:39 +0800, Zhao, Yakui wrote:
On Tue, 2014-05-27 at 02:59 -0600, Zhao, Halley wrote:
From: Zhao, Halley halley.z...@intel.com
VA_INTEL_DEBUG_ASSERT decides assert() is enabled
On Wed, 2014-05-28 at 10:54 +0800, Zhao, Halley wrote:
From: Zhao, Halley halley.z...@intel.com
Looks good to me.
Add: Reviewed-by: Zhao, Yakui yakui.z...@intel.com
Thanks.
Yakui
VA_INTEL_DEBUG_ASSERT decides assert() is enabled or not
VA_INTEL_DEBUG_BENCH decides skip putsurface
On Wed, 2014-05-28 at 10:10 +0300, sreerenj.balachand...@intel.com
wrote:
From: Sreerenj Balachandran sreerenj.balachand...@intel.com
Avoid storing packed slice header index as packed raw data index.
This is necessary for handling the use case of having
only packed slice header and no packed
On Wed, 2014-05-28 at 11:14 +0300, Sreerenj wrote:
Hi,
On 28.05.2014 11:07, Zhao, Yakui wrote:
On Wed, 2014-05-28 at 10:10 +0300, sreerenj.balachand...@intel.com
wrote:
From: Sreerenj Balachandran sreerenj.balachand...@intel.com
Avoid storing packed slice header index as packed raw
On Wed, 2014-05-28 at 15:02 -0600, sreerenj.balachand...@intel.com
wrote:
From: Sreerenj Balachandran sreerenj.balachand...@intel.com
Avoid storing packed slice header index as packed raw data index.
This patch is a preparation for submitting all the packed slice
headers as a group , instead
On Fri, 2014-05-30 at 11:06 +0300, Sreerenj wrote:
On 29.05.2014 03:42, Zhao, Yakui wrote:
On Wed, 2014-05-28 at 15:02 -0600, sreerenj.balachand...@intel.com
wrote:
From: Sreerenj Balachandran sreerenj.balachand...@intel.com
Avoid storing packed slice header index as packed raw data
On Fri, 2014-05-30 at 03:30 -0600, Balachandran, Sreerenj wrote:
On 30.05.2014 11:48, Zhao, Yakui wrote:
On Fri, 2014-05-30 at 11:06 +0300, Sreerenj wrote:
On 29.05.2014 03:42, Zhao, Yakui wrote:
On Wed, 2014-05-28 at 15:02 -0600, sreerenj.balachand...@intel.com
wrote:
From: Sreerenj
On Mon, 2014-06-02 at 11:58 -0600, Gwenole Beauchesne wrote:
This is a convenience to use the GenFrameStoreContext structure,
when the whole frame store machinery is maintain. No functional
change.
Signed-off-by: Gwenole Beauchesne gwenole.beauche...@intel.com
---
src/gen6_mfd.c
On Tue, 2014-06-03 at 10:43 -0600, Gwenole Beauchesne wrote:
If the RefPicListX[] entry has no valid picture_id associated to it,
then set the resulting state to 0xff. If that entry has no surface
buffer storage either, then compose a valid state that maps to the
first item in the reference
On Tue, 2014-06-03 at 10:43 -0600, Gwenole Beauchesne wrote:
Fill and submit MFX_AVC_PICID_STATE commands to Gen7.5+ hardware.
This optimizes the management of the DPB as the binding array can
now contain entries in any order. This also makes it possible to
support H.264 MultiView High
On Tue, 2014-06-03 at 10:43 -0600, Gwenole Beauchesne wrote:
Simplify and optimize the update process of the reference frame store.
Use less iterations to look up existing objects. Use a cache to store
the free'd slots.
Prerequisite: the reference_objects[] array was previously arranged in
On Mon, 2014-06-02 at 23:03 -0600, Gwenole Beauchesne wrote:
2014-06-03 5:10 GMT+02:00 Zhao, Yakui yakui.z...@intel.com:
On Mon, 2014-06-02 at 11:58 -0600, Gwenole Beauchesne wrote:
Hi,
This patch series adds support for H.264 Multiview High profile on
Haswell and newer generations
On Tue, 2014-06-03 at 22:59 -0600, Gwenole Beauchesne wrote:
2014-06-04 4:11 GMT+02:00 Zhao, Yakui yakui.z...@intel.com:
On Tue, 2014-06-03 at 10:43 -0600, Gwenole Beauchesne wrote:
Simplify and optimize the update process of the reference frame store.
Use less iterations to look up
From: Zhao, Yakui yakui.z...@intel.com
Signed-off-by: Zhao, Yakui yakui.z...@intel.com
---
src/i965_drv_video.h | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/src/i965_drv_video.h b/src/i965_drv_video.h
index 418c277..fff301c 100644
--- a/src/i965_drv_video.h
+++ b
On Thu, 2014-06-05 at 10:20 -0600, Gwenole Beauchesne wrote:
2014-06-05 17:29 GMT+02:00 Xiang, Haihao haihao.xi...@intel.com:
-Original Message-
From: Gwenole Beauchesne [mailto:gb.de...@gmail.com]
Sent: Thursday, June 05, 2014 9:29 PM
To: Xiang, Haihao
Cc: Zhao, Yakui
On Thu, 2014-06-05 at 17:46 -0600, Gwenole Beauchesne wrote:
In strict MVC decoding mode, when only the necessary set of inter-view
reference pictures are passed to the ReferenceFrames array for decoding
the current picture, we should not re-use a frame store id that might
be needed for
On Fri, 2014-06-06 at 02:02 -0600, Gwenole Beauchesne wrote:
2014-06-06 9:59 GMT+02:00 Gwenole Beauchesne gb.de...@gmail.com:
Hi,
2014-06-06 8:27 GMT+02:00 Zhao, Yakui yakui.z...@intel.com:
On Thu, 2014-06-05 at 17:46 -0600, Gwenole Beauchesne wrote:
In strict MVC decoding mode, when
From: Zhao, Yakui yakui.z...@intel.com
Otherwise it will cause the incorrect intra-prediction for encoding on
Broadwell.
Signed-off-by: Zhao Yakui yakui.z...@intel.com
---
src/shaders/vme/intra_frame_gen8.asm | 2 +-
src/shaders/vme/intra_frame_gen8.g8b | 2 +-
2 files changed, 2 insertions
On Sun, 2014-06-08 at 22:11 -0600, Zhao, Yakui wrote:
From: Zhao, Yakui yakui.z...@intel.com
Otherwise it will cause the incorrect intra-prediction for encoding on
Broadwell.
This is pushed to the staging branch.
Thanks.
Yakui
Signed-off-by: Zhao Yakui yakui.z...@intel.com
---
src
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