On Thu, Oct 19, 2023 at 1:47 AM Rob Bradford wrote:
>
> This has been replaced by a "pmu-mask" property that provides much more
> flexibility.
>
> Signed-off-by: Rob Bradford
> Acked-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Alistair
> ---
&g
On Thu, Oct 12, 2023 at 12:52 AM Rob Bradford wrote:
>
> This has been replaced by a "pmu-mask" property that provides much more
> flexibility.
>
> Signed-off-by: Rob Bradford
> ---
> docs/about/deprecated.rst | 10 ++
> 1 file changed, 10 insertions(+)
>
> diff --git
On Wed, Jan 12, 2022 at 6:20 PM Yifei Jiang via wrote:
>
> This series adds both riscv32 and riscv64 kvm support, and implements
> migration based on riscv.
>
> Because of RISC-V KVM has been merged into the Linux master, so this
> series are changed from RFC to patch.
>
> Several steps to use
On Wed, Jan 12, 2022 at 6:25 PM Yifei Jiang via wrote:
>
> Add riscv kvm support in meson.build file.
>
> Signed-off-by: Yifei Jiang
> Signed-off-by: Mingwang Li
Reviewed-by: Alistair Francis
Alistair
> ---
> meson.build | 2 ++
> 1 file changed, 2 inse
ed.
>
> Signed-off-by: Yifei Jiang
> Signed-off-by: Mingwang Li
> Reviewed-by: Alistair Francis
> ---
> hw/intc/sifive_plic.c| 21 +++---
> hw/riscv/boot.c | 16 +++-
> hw/riscv/virt.c | 83
> include/
On Mon, Jan 10, 2022 at 11:48 AM Yifei Jiang via wrote:
>
> Add target/riscv/kvm.c to place kvm_arch_* function needed by
> kvm/kvm-all.c. Meanwhile, add kvm support in meson.build file.
>
> Signed-off-by: Yifei Jiang
> Signed-off-by: Mingwang Li
> Reviewed-by: Alistai
On Mon, Jan 10, 2022 at 11:57 AM Yifei Jiang via wrote:
>
> Put GPR CSR and FP registers to kvm by KVM_SET_ONE_REG ioctl
>
> Signed-off-by: Yifei Jiang
> Signed-off-by: Mingwang Li
> Reviewed-by: Alistair Francis
> Reviewed-by: Anup Patel
> ---
>
it doesn't matter
> that adaping in QEMU.
>
> Signed-off-by: Yifei Jiang
> Signed-off-by: Mingwang Li
> Reviewed-by: Anup Patel
Acked-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.h | 7 +
> target/riscv/kvm.c | 72 ++
On Mon, Jan 10, 2022 at 11:49 AM Yifei Jiang via wrote:
>
> Use char-fe to handle console sbi call, which implement early
> console io while apply 'earlycon=sbi' into kernel parameters.
>
> Signed-off-by: Yifei Jiang
> Signed-off-by: Mingwang Li
> Reviewed-by: Anup Patel
On Tue, Dec 21, 2021 at 2:44 AM Yifei Jiang via wrote:
>
> Add virtual time context description to vmstate_kvmtimer. After cpu being
> loaded, virtual time context is updated to KVM.
>
> Signed-off-by: Yifei Jiang
> Signed-off-by: Mingwang Li
> Reviewed-by: Anup Patel
ntinue to count and kvm_timer should be restored.
>
> Signed-off-by: Yifei Jiang
> Signed-off-by: Mingwang Li
> Reviewed-by: Anup Patel
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/kvm.c | 14 ++
> 1 file changed, 14 insertions(+)
>
> diff --git
On Tue, Dec 21, 2021 at 3:41 AM Yifei Jiang via wrote:
>
> Use char-fe to handle console sbi call, which implement early
> console io while apply 'earlycon=sbi' into kernel parameters.
>
> Signed-off-by: Yifei Jiang
> Signed-off-by: Mingwang Li
> Reviewed-by: Anup Patel
> ---
>
On Sat, Nov 20, 2021 at 5:51 PM Yifei Jiang wrote:
>
> Add asm-riscv/kvm.h for RISC-V KVM, and update linux/kvm.h
>
> Signed-off-by: Yifei Jiang
> Signed-off-by: Mingwang Li
Acked-by: Alistair Francis
Alistair
> ---
> linux-headers/
On Tue, Aug 17, 2021 at 1:25 PM Yifei Jiang wrote:
>
> Use char-fe to handle console sbi call, which implement early
> console io while apply 'earlycon=sbi' into kernel parameters.
>
> Signed-off-by: Yifei Jiang
> Signed-off-by: Mingwang Li
> ---
> target/riscv/kvm.c | 42
On Mon, Apr 12, 2021 at 4:57 PM Yifei Jiang wrote:
>
> Only support supervisor external interrupt currently.
>
> Signed-off-by: Yifei Jiang
> Signed-off-by: Yipeng Yin
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/intc/sifive_plic.c| 29
On Mon, Apr 12, 2021 at 4:56 PM Yifei Jiang wrote:
>
> Get kernel and fdt start address in virt.c, and pass them to KVM
> when cpu reset. In addition, add kvm_riscv.h to place riscv specific
> interface.
>
> Signed-off-by: Yifei Jiang
> Signed-off-by: Yipeng Yin
Reviewed
; +reg = env->sbadaddr;
This will change soon-ish as my next PR converts this to stval.
> +ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, stval), );
> +if (ret) {
> +return ret;
> +}
> +
> +reg = env->mip;
> + ret = kvm_set_one_reg(cs, RISCV
On Mon, Apr 12, 2021 at 4:58 PM Yifei Jiang wrote:
>
> Get GPR CSR and FP registers from kvm by KVM_GET_ONE_REG ioctl.
>
> Signed-off-by: Yifei Jiang
> Signed-off-by: Yipeng Yin
Reviewed-by: Alistair Francis
Alistair
> ---
> tar
scv_reg_id(CPURISCVState *env, __u64 type, __u64 idx)
> +{
> +__u64 id = KVM_REG_RISCV | type | idx;
Can you use uint64_t instead of __u64?
Once that is fixed:
Reviewed-by: Alistair Francis
Alistair
> +
> +if (riscv_cpu_is_32bit(env)) {
> +id |= KVM_REG_SIZE_U32;
> +
On Mon, Apr 12, 2021 at 4:54 PM Yifei Jiang wrote:
>
> 'host' type cpu is set isa to RVXLEN simply, more isa info
> will obtain from KVM in kvm_arch_init_vcpu()
>
> Signed-off-by: Yifei Jiang
> Signed-off-by: Yipeng Yin
Reviewed-by: Alistair Francis
Alistair
> ---
>
On Mon, Dec 14, 2020 at 11:31 PM Jiangyifei wrote:
>
>
> > -Original Message-
> > From: Alistair Francis [mailto:alistai...@gmail.com]
> > Sent: Wednesday, December 9, 2020 6:26 AM
> > To: Jiangyifei
> > Cc: qemu-de...@nongnu.org Developers ; ope
On Thu, Dec 3, 2020 at 4:47 AM Yifei Jiang wrote:
>
> Only support supervisor external interrupt currently.
>
> Signed-off-by: Yifei Jiang
> Signed-off-by: Yipeng Yin
> ---
> hw/intc/sifive_plic.c| 31 ++-
> target/riscv/kvm.c | 19 +++
>
On Thu, Dec 3, 2020 at 4:57 AM Yifei Jiang wrote:
>
> Currently, time base frequency was fixed as SIFIVE_CLINT_TIMEBASE_FREQ.
> Here introduce "time-frequency" property to set time base frequency
> dynamically
> of which default value is still SIFIVE_CLINT_TIMEBASE_FREQ. The virt machine
> uses
On Thu, Dec 3, 2020 at 4:55 AM Yifei Jiang wrote:
>
> Currently, host cpu is inherited simply.
>
> Signed-off-by: Yifei Jiang
> Signed-off-by: Yipeng Yin
> ---
> target/riscv/cpu.c | 6 ++
> target/riscv/cpu.h | 1 +
> 2 files changed, 7 insertions(+)
>
> diff --git a/target/riscv/cpu.c
On Thu, Dec 3, 2020 at 4:58 AM Yifei Jiang wrote:
>
> Get kernel and fdt start address in virt.c, and pass them to KVM
> when cpu reset. In addition, add kvm_riscv.h to place riscv specific
> interface.
This doesn't seem right. Why do we need to do this? Other
architectures don't seem to do
On Thu, Dec 3, 2020 at 4:55 AM Yifei Jiang wrote:
>
> Get isa info from kvm while kvm init.
>
> Signed-off-by: Yifei Jiang
> Signed-off-by: Yipeng Yin
> ---
> target/riscv/kvm.c | 27 ++-
> 1 file changed, 26 insertions(+), 1 deletion(-)
>
> diff --git
On Sun, Jul 5, 2020 at 3:08 PM Philippe Mathieu-Daudé wrote:
>
> I tried to maintain the SPI mode because it is useful in
> tiny embedded devices, and thought it would be helpful for
> the AVR MCUs.
> As AVR was blocked, I thought it was wise to deprecate the
> SPI mode as users are interested in
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