hi Martin,
Thanks for reaching me, sure, I will try to testing your patch.
BTW, do you have a github repo/branch for these which I can directly pull?
Best regards
- Eli
a leaf duckweed belongs to the sea, where not to meet in life
2017-12-13 23:39 GMT+08:00 Martin Kletzander
>
>
>
> We didn't want to exec external python programs because that certainly
> *does* have bad scalability, terrible error reporting facilities and
> need to parse ill defined data formats from stdout, etc. It doesn't
> magically solve the complexity, just moves it elsewhere where we have
> less
2017-09-04 23:57 GMT+08:00 Daniel P. Berrange :
> On Mon, Sep 04, 2017 at 04:14:00PM +0200, Martin Kletzander wrote:
> > * The current design (finally something libvirt-related, right?)
> >
> > The discussion ended with a conclusion of the following (with my best
> >
ping
On Wednesday, 5 July 2017 at 10:39 AM, Eli Qiao wrote:
> Allow user to define cachetune in domain xml.
>
> RESEND:
> * Fix stupid complile problem pointed out by Martin, check and syntax-check
> passed.
>
> V2 -> V1 changes:
> * Redefine cachetune xml in doma
to minimum.
vcpus: cache allocation on vcpu set, if empty, will apply the allocation
on all vcpus.
Signed-off-by: Eli Qiao <liyong.q...@intel.com>
---
docs/schemas/domaincommon.rng | 29 +++
src/conf/domain_conf.c| 112 +
Allow user to define cachetune in domain xml.
RESEND:
* Fix stupid complile problem pointed out by Martin, check and syntax-check
passed.
V2 -> V1 changes:
* Redefine cachetune xml in domain xml.
* Create a struct for driver to talk with util/virresctrl.*
* Nit fixes
Eli Qiao
.
virResctrlRemoveCachetunes: remove cache allocation group from the
host.
Signed-off-by: Eli Qiao <liyong.q...@intel.com>
---
include/libvirt/virterror.h | 1 +
src/Makefile.am | 1 +
src/libvirt_privat
On Friday, 30 June 2017 at 7:06 PM, Martin Kletzander wrote:
> On Mon, Jun 26, 2017 at 06:33:39PM +0800, Eli Qiao wrote:
> > This patch adds new xml element to support cache tune as:
> >
> >
> > ...
> >
> > ...
> >
> >
> > c
Allow user to define cachetune in domain xml.
V2 -> V1 changes:
* Redefine cachetune xml in domain xml.
* Create a struct for driver to talk with util/virresctrl.*
* Nit fixes
Eli Qiao (2):
Resctrl: Add new xml element to support cache tune
Resctrl: Do cache allocation while b
.
virResctrlRemoveCachetunes: remove cache allocation group from the
host.
Signed-off-by: Eli Qiao <liyong.q...@intel.com>
---
include/libvirt/virterror.h | 1 +
src/Makefile.am | 1 +
src/libvirt_privat
to minimum.
vcpus: cache allocation on vcpu set, if empty, will apply the allocation
on all vcpus.
Signed-off-by: Eli Qiao <liyong.q...@intel.com>
---
docs/schemas/domaincommon.rng | 29 +++
src/conf/domain_conf.c| 113 +
On Thursday, 22 June 2017 at 8:41 PM, Martin Kletzander wrote:
> I missed this. Ye, you're right, thanks for showing that with a use
> case. We could then require only the cache_id and automatically fill
> in level and type. Migration (or rather any start) should then fail if
> that cache_id
On Wednesday, 21 June 2017 at 10:44 PM, Martin Kletzander wrote:
> n 21, 2017 at 02:07:15PM +0800, Eli Qiao wrote:
>
> You don't need to pass the whole structure of all the data. Can't the
> qemu function just do something like:
>
> virResctrlLock()
> foreac
On Wednesday, 21 June 2017 at 10:44 PM, Martin Kletzander wrote:
> You don't need to pass the whole structure of all the data. Can't the
> qemu function just do something like:
>
> virResctrlLock()
> foreach cachetune:
> region = virResctrlGetFreeRegion(size, type)
> foreach cachetune.vcpu:
>
hi Martin
It’s really nice of you to help reviewing the mass code. Thanks.
I don’t find a better way to split patch.
On Wednesday, 21 June 2017 at 9:53 PM, Martin Kletzander wrote:
> On Mon, Jun 12, 2017 at 05:48:40PM +0800, Eli Qiao wrote:
> > This patch adds new xml element t
On Tuesday, 20 June 2017 at 8:39 PM, Martin Kletzander wrote:
> On Mon, Jun 12, 2017 at 05:48:41PM +0800, Eli Qiao wrote:
> > This patch adds 3 major private interface.
> >
> > virResctrlGetFreeCache: return free cache, default cache substract cache
> > allocated.
hello,
ping
On Monday, 12 June 2017 at 5:48 PM, Eli Qiao wrote:
> This patch adds 3 major private interface.
>
> virResctrlGetFreeCache: return free cache, default cache substract cache
> allocated.
> virResctrlSetCachetunes: set cache banks which defi
allocation on vcpu set, if empty, will apply the allocation
on all vcpus
Signed-off-by: Eli Qiao <liyong.q...@intel.com>
---
docs/schemas/domaincommon.rng | 54 +
src/conf/domain_conf.c| 131 ++
src/conf/domain_conf.h
://www.kernel.org/doc/Documentation/x86/intel_rdt_ui.txt
[4] https://github.com/taget/libvirt/commits/cache
Eli Qiao (2):
Resctrl: Add new xml element to support cache tune
Resctrl: Add uitls functions to operate sysfs resctrl
docs/schemas/domaincommon.rng | 54 ++
include/libvirt
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this
Thanks martin,
Looks good to me.
On Friday, 9 June 2017 at 4:52 PM, Martin Kletzander wrote:
> On some platforms the number of bits in the cbm_mask might not be
> divisible by 4 (and not even by 2), so we need to properly count the
> bits. Similar file, min_cbm_bits, is properly parsed and
> >
> > This could be wrong on new platform in Intel’s SKX CPU after check with
> > platform guys.
> >
> > The cbm_mask is “7ff” (11 bits) on SKX. I will refine this by counting the
> > bits.
> >
> > We can virFileReadValueString() then convert it to unsigned int, then count
> > the bits
hi Martin
The code looks good to me, I have 1 comment for the granularity’s comment, and
another one for the test data.
Otherwise, looks perfect, good to learn how to deal with hex
On Monday, 5 June 2017 at 9:14 PM, Martin Kletzander wrote:
> On some platforms the number of bits in the
updated.
Signed-off-by: Eli Qiao <qiaoliy...@gmail.com>
---
docs/schemas/capability.rng | 3 +++
src/conf/capabilities.c | 19 ---
src/conf/capabilities.h | 1 +
.../linux-resctrl/resctr
Martin:
Please hold on merge this first.
I found we still need some modification.
> >
> > Again, wrong indentation and unnecessary parentheses.
> >
> > Otherwise it looks good, so ACK with those differences and reworded
> > commit message. Let me know if you agree and I can push it
hi Martin
Thanks for you reviewing and I am okay with the diff as you suggested.
Please help to push this patch.
Eli.
On Sunday, 4 June 2017 at 5:39 PM, Martin Kletzander wrote:
> On Wed, May 17, 2017 at 05:08:33PM +0800, taget wrote:
> > From: Eli Qiao <liyong.q.
From: Eli Qiao <liyong.q...@intel.com>
This is a RFC patch for the reimplement of `support cache tune(CAT) in
libvirt`[1].
This patch defines some structs to represent data struct in linux
resctrl fs which will be used later to do cache allocation.
The patch expose a private int
ping
On Wednesday, 17 May 2017 at 5:08 PM, taget wrote:
> From: Eli Qiao <liyong.q...@intel.com (mailto:liyong.q...@intel.com)>
>
> * This patch amends the cache bank capability as follow:
>
>
>
>
>
>
>
>
>
>
* This patch amends the cache bank capability as follow:
For CDP enabled on x86 arch, we will have:
...
* Added a new testdata directory `linux-resctrl-cdp` to test CDP enabled
case.
* Along with vircaps2xmltest case updated.
Signed-off-by: Eli Qiao
On Wednesday, 3 May 2017 at 4:34 PM, Daniel P. Berrange wrote:
> On Wed, May 03, 2017 at 08:30:31AM +0800, Eli Qiao wrote:
> > hi all,
> >
> > Thanks for helping reviewing for CAT support in the past days.
> >
> > I writing this email to ask for the pla
hi all,
Thanks for helping reviewing for CAT support in the past days.
I writing this email to ask for the plan in libvirt support.
I think we’v discussed this early this year, and I’v proposed a patch set [1].
But don’t get merged because of some performance reason ?
Then I proposed a
/sys/fs/resctrl ?
On Friday, 28 April 2017 at 8:16 PM, Martin Kletzander wrote:
> On Fri, Apr 14, 2017 at 06:01:46PM +0800, Eli Qiao wrote:
> > This is a RFC patch for the reimplement of `support cache tune(CAT) in
> > libvirt`[1].
> >
>
>
> I searched for
Ping
Please let me know which is the direction.
Thx.
On Friday, 14 April 2017 at 6:01 PM, Eli Qiao wrote:
> This is a RFC patch for the reimplement of `support cache tune(CAT) in
> libvirt`[1].
>
> This patch defines some structs to represent data struct in linux
> r
* <http://www.gnu.org/licenses/>.
+ *
+ * Authors:
+ * Eli Qiao <liyong.q...@intel.com>
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "virresctrl.h"
+#include "virerror.h"
+#include "virlog.h"
+#include "viralloc.h
General Public
+ * License along with this library. If not, see
+ * <http://www.gnu.org/licenses/>.
+ *
+ * Authors:
+ * Eli Qiao <liyong.q...@intel.com>
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "virresctrl.h"
+#include "viralloc.h"
with vircaps2xmltest case updated.
P.S. here the scope is from /sys/fs/resctrl/info/L3{"" "code" "data"}, I
keep it capital upper as I need to use a macro to convert from enum to
string easily.
Signed-off-by: Eli Qiao <liyong.q...@intel.com>
---
docs/schemas/capability.rng
On Tuesday, 11 April 2017 at 4:10 PM, Martin Kletzander wrote:
> This should just be:
>
> + if (virAsprintf(, "%s/vircaps2xmldata/linux-%s/resctrl",
> + abs_srcdir, data->filename) < 0)
>
yep, stupid me. I get it now. --
libvir-list mailing list
libvir-list@redhat.com
On Tuesday, 11 April 2017 at 3:48 PM, Peter Krempa wrote:
> On Tue, Apr 11, 2017 at 13:44:26 +0800, Eli Qiao wrote:
> > This patch is based on Martin's cache branch.
> >
> > * This patch amends the cache bank
> >
> >
> >
> >
> >
> > @Daniel,
> >
> > the enum values are same with `type`
> >
> > unified: 0
> > instruction: 1
> > data: 2
> >
> > but scope should be both(0)/code(1)/data(2), so the attribute name will be
>
> 'both' and 'unified' mean the same thing.
>
> 'instruction'
with vircaps2xmltest case updated.
P.S. here the scope is from /sys/fs/resctrl/info/L3{"" "CODE" "DATA"}, I
keep it capital upper as I need to use a macro to convert from enum to
string easily.
Signed-off-by: Eli Qiao <liyong.q...@intel.com>
---
docs/schemas/capability.rng
On Friday, 7 April 2017 at 7:06 PM, Daniel P. Berrange wrote:
> On Fri, Apr 07, 2017 at 01:04:57PM +0200, Martin Kletzander wrote:
> > On Fri, Apr 07, 2017 at 05:47:54PM +0800, Eli Qiao wrote:
> > > >
> > > > The name doesn't really matter that much, 'scop
>
> The name doesn't really matter that much, 'scope' makes a bit more
> sense, 'type' is consistent with the cache bank specification, I'm fine
> with any. The big question here was if it is possible to have:
>
>
>
>
>
>
> And from what you say, the simple answer is "yes". So we need to
On Thursday, 6 April 2017 at 9:04 PM, Martin Kletzander wrote:
> On Thu, Apr 06, 2017 at 01:25:35PM +0100, Daniel P. Berrange wrote:
> > On Thu, Apr 06, 2017 at 08:20:56PM +0800, Eli Qiao wrote:
> > > This patch is based on Martin's cache branch.
> > >
> > &
On Thursday, 6 April 2017 at 8:46 PM, Martin Kletzander wrote:
> On Thu, Apr 06, 2017 at 08:20:56PM +0800, Eli Qiao wrote:
> > This patch is based on Martin's cache branch.
> >
> > This patch amends the cache bank capability as follow:
>
> It helps a lot i
This patch is based on Martin's cache branch.
This patch amends the cache bank capability as follow:
Along with vircaps2xmltest case updated.
Signed-off-by: Eli Qiao <liyong.q...@intel.com>
---
src/conf/capabilities.c
On Thursday, 6 April 2017 at 7:56 PM, Daniel P. Berrange wrote:
> On Thu, Apr 06, 2017 at 07:32:59PM +0800, Eli Qiao wrote:
> > This patch is based on Martin's cache branch.
> >
> > This patch amends the cache bank
This patch is based on Martin's cache branch.
This patch amends the cache bank capability as follow:
Along with vircaps2xmltest case updated.
Signed-off-by: Eli Qiao <liyong.q...@intel.com>
---
src/conf/capabilities.c
On Thursday, 6 April 2017 at 5:51 PM, Daniel P. Berrange wrote:
> On Thu, Apr 06, 2017 at 11:49:14AM +0200, Martin Kletzander wrote:
> > On Thu, Apr 06, 2017 at 04:20:06PM +0800, Eli Qiao wrote:
> > > This patch is based on Martin's cache branch.
> > >
> > &
On Thursday, 6 April 2017 at 5:49 PM, Martin Kletzander wrote:
> On Thu, Apr 06, 2017 at 04:20:06PM +0800, Eli Qiao wrote:
> > This patch is based on Martin's cache branch.
> >
> > This patch amends the cache bank capability as follow:
> >
> >
>
On Thursday, 6 April 2017 at 5:49 PM, Martin Kletzander wrote:
> On Thu, Apr 06, 2017 at 04:20:06PM +0800, Eli Qiao wrote:
> > This patch is based on Martin's cache branch.
> >
> > This patch amends the cache bank capability as follow:
> >
> >
>
te:
> > > > On Thu, Apr 06, 2017 at 04:20:06PM +0800, Eli Qiao wrote:
> > > > > This patch is based on Martin's cache branch.
> > > > >
> > > > > This patch amends the cache bank capability as follow:
> >
This patch is based on Martin's cache branch.
This patch amends the cache bank capability as follow:
Along with vircaps2xmltest case updated.
Signed-off-by: Eli Qiao <liyong.q...@intel.com>
---
src/conf/capabilities.c | 112 +--
sr
> +
> +VIR_ENUM_IMPL(virCache, VIR_CACHE_TYPE_LAST,
> + "unified",
> + "instruction",
> + "data")
> +
> };
>
> +typedef enum {
> + VIR_CACHE_TYPE_DATA,
> + VIR_CACHE_TYPE_INSTRUCTION,
> + VIR_CACHE_TYPE_UNIFIED,
> +
> + VIR_CACHE_TYPE_LAST
> +} virCacheType;
> +
The sequence is wrong, it
On Wednesday, 5 April 2017 at 10:36 PM, Martin Kletzander wrote:
> Add info from yet another machine, this time with resctrl data so that
> we can extend tests easily in a test-driven way.
>
> Signed-off-by: Martin Kletzander (mailto:mklet...@redhat.com)>
> ---
>
> >
> > How about for l3:
> > > reserved=“2816"/>
> >
>
>
> Well, yes, kind of what you had in your patches. Wasn't it without the
> 'cbm_len' and 'avail'? The 'cbm_len' is avail/min, so it's redundant
> and avail is the same as the size of the whole cache, right? Also
> 'reserved'
On Friday, 31 March 2017 at 7:39 PM, Martin Kletzander wrote:
> On Fri, Mar 31, 2017 at 05:32:16PM +0800, Eli Qiao wrote:
> >
> >
> > On Thursday, 30 March 2017 at 10:03 PM, Martin Kletzander wrote:
> >
> > > Signed-off-by: Martin Kletzander <m
On Friday, 31 March 2017 at 7:19 PM, Martin Kletzander wrote:
> On Fri, Mar 31, 2017 at 09:56:32AM +0800, Eli Qiao wrote:
> >
> > >
> > Okay, cool, this comes better than my patches and have some differences.
> > I am open with this as long as that it can
Extended /sys/fs/resctrl sysfs handling such as:
Read string/uint.
Write string.
Create/remove directory.
All these operations will be while we are enabled CAT feature later.
Signed-off-by: Eli Qiao <liyong.q...@intel.com>
---
src/libvirt_private.syms | 9 +++
src/util/virs
On Thursday, 30 March 2017 at 10:03 PM, Martin Kletzander wrote:
> Signed-off-by: Martin Kletzander (mailto:mklet...@redhat.com)>
> ---
> src/libvirt_private.syms | 5 +++
> src/util/virsysfs.c | 102 +++
> src/util/virsysfs.h |
>
Okay, cool, this comes better than my patches and have some differences.
I am open with this as long as that it can meet cache allocation requires and
everyone will be happy.
I am ++ for this.
But I am not sure expose all of cache information in the capabilities XML.
>
> +
> +
>
>
On Thursday, 30 March 2017 at 10:03 PM, Martin Kletzander wrote:
> Signed-off-by: Martin Kletzander (mailto:mklet...@redhat.com)>
> ---
> src/libvirt_private.syms | 1 +
> src/util/virsysfs.c | 17 -
> src/util/virsysfs.h | 6 ++
> 3 files changed, 23
> > +# util/virresctrl.h
> > +virResCtrlAvailable;
> > +virResCtrlInit;
> > +
> >
>
>
> This has nothing to do in the patch
>
Okay, this should be involved by mistake while rebasing.
>
> > # util/virrotatingfile.h
> > virRotatingFileReaderConsume;
> > virRotatingFileReaderFree;
> > @@
Added fake cpu cache id and resctrl file
Signed-off-by: Eli Qiao <liyong.q...@intel.com>
---
tests/vircaps2xmldata/linux-caches/cpu/cpu0/cache/index0/id | 1 +
tests/vircaps2xmldata/linux-caches/cpu/cpu0/cache/index1/id | 1 +
tests/vircaps2xmldata/linux-caches/cpu/cpu0/cache/index2/
Extended /sys/fs/resctrl sysfs handling.
Signed-off-by: Eli Qiao <liyong.q...@intel.com>
---
src/libvirt_private.syms | 11 -
src/util/virsysfs.c | 102 ++-
src/util/virsysfs.h | 16
src/util/virsysfspriv.h | 1 +
4
On Wednesday, 29 March 2017 at 5:47 PM, Martin Kletzander wrote:
> On Wed, Mar 29, 2017 at 05:31:42PM +0800, Eli Qiao wrote:
> >
> >
> > --
> > Best regards
> > Eli
> >
> > 天涯无处不重逢
> > a leaf duckweed belongs to the sea, where no
Added fake cpu cache id and resctrl file
Signed-off-by: Eli Qiao <liyong.q...@intel.com>
---
tests/vircaps2xmldata/linux-caches/cpu/cpu0/cache/index0/id | 1 +
tests/vircaps2xmldata/linux-caches/cpu/cpu0/cache/index1/id | 1 +
tests/vircaps2xmldata/linux-caches/cpu/cpu0/cache/index2/
Extended /sys/fs/resctrl sysfs handling.
Signed-off-by: Eli Qiao <liyong.q...@intel.com>
---
src/libvirt_private.syms | 4 ++
src/util/virsysfs.c | 98 +++-
src/util/virsysfs.h | 15
3 files changed, 116 insertions(+), 1 de
--
Best regards
Eli
天涯无处不重逢
a leaf duckweed belongs to the sea, where not to meet in life
Sent with Sparrow (http://www.sparrowmailapp.com/?sig)
On Wednesday, 29 March 2017 at 5:19 PM, Martin Kletzander wrote:
> On Wed, Mar 29, 2017 at 04:22:16PM +0800, Eli Qiao wr
--
Best regards
Eli
天涯无处不重逢
a leaf duckweed belongs to the sea, where not to meet in life
Sent with Sparrow (http://www.sparrowmailapp.com/?sig)
On Wednesday, 29 March 2017 at 3:45 PM, Martin Kletzander wrote:
> On Tue, Mar 28, 2017 at 03:22:34PM +0800, Eli Qiao wrote:
> >
with Sparrow (http://www.sparrowmailapp.com/?sig)
On Friday, 24 March 2017 at 3:42 PM, Martin Kletzander wrote:
> On Fri, Mar 24, 2017 at 09:35:33AM +0800, Eli Qiao wrote:
> >
> >
> > --
> > Best regards
> > Eli
> >
> > 天涯无处不重逢
> > a
--
Best regards
Eli
天涯无处不重逢
a leaf duckweed belongs to the sea, where not to meet in life
Sent with Sparrow (http://www.sparrowmailapp.com/?sig)
On Thursday, 16 March 2017 at 3:52 PM, Eli Qiao wrote:
>
>
> --
> Best regards
> Eli
>
> 天涯无处不重逢
>
--
Best regards
Eli
天涯无处不重逢
a leaf duckweed belongs to the sea, where not to meet in life
Sent with Sparrow (http://www.sparrowmailapp.com/?sig)
On Wednesday, 15 March 2017 at 8:53 PM, Martin Kletzander wrote:
> On Mon, Mar 06, 2017 at 06:06:31PM +0800, Eli Qiao wrote:
> > T
--
Best regards
Eli
天涯无处不重逢
a leaf duckweed belongs to the sea, where not to meet in life
Sent with Sparrow (http://www.sparrowmailapp.com/?sig)
On Wednesday, 15 March 2017 at 7:57 PM, Martin Kletzander wrote:
> On Mon, Mar 06, 2017 at 06:06:30PM +0800, Eli Qiao wrote:
> > T
--
Best regards
Eli
天涯无处不重逢
a leaf duckweed belongs to the sea, where not to meet in life
Sent with Sparrow (http://www.sparrowmailapp.com/?sig)
On Wednesday, 15 March 2017 at 8:20 PM, Martin Kletzander wrote:
> On Mon, Mar 06, 2017 at 06:06:30PM +0800, Eli Qiao wrote:
> > T
--
Best regards
Eli
天涯无处不重逢
a leaf duckweed belongs to the sea, where not to meet in life
Sent with Sparrow (http://www.sparrowmailapp.com/?sig)
On Tuesday, 7 March 2017 at 5:33 AM, Marcelo Tosatti wrote:
> On Mon, Mar 06, 2017 at 05:50:43PM +0800, Eli Qiao wrote:
> > Add
This patch support l3 cache allocation compatible mode if cdp enabled
on host.
In this case l3code/l3data has same schemata.
Signed-off-by: Eli Qiao <liyong.q...@intel.com>
---
src/conf/domain_conf.c | 15 +--
src/util/virresctrl.c | 10 ++
2 files changed, 23 inse
resctrl -o cdp /sys/fs/resctrl
Signed-off-by: Eli Qiao <liyong.q...@intel.com>
---
docs/schemas/domaincommon.rng | 2 +-
src/util/virresctrl.c | 27 +--
2 files changed, 26 insertions(+), 3 deletions(-)
diff --git a/docs/schemas/domaincommon.rng b/docs/s
directory, and update the schemata
after libvirt domain destroy.
Signed-off-by: Eli Qiao <liyong.q...@intel.com>
---
src/libvirt_private.syms | 6 +-
src/util/virresctrl.c| 677 +++
src/util/virresctrl.h| 5 +-
3
This patch support l3 cache allocation compatible mode if cdp enabled
on host.
In this case l3code/l3data has same schemata.
Signed-off-by: Eli Qiao <liyong.q...@intel.com>
---
src/conf/domain_conf.c | 15 +--
src/util/virresctrl.c | 10 ++
2 files changed, 23 inse
l3data and l3code type of cache banks should be configured pairs.
Signed-off-by: Eli Qiao <liyong.q...@intel.com>
---
src/conf/domain_conf.c | 19 +++
src/util/virresctrl.c | 1 -
src/util/virresctrl.h | 2 ++
3 files changed, 21 insertions(+), 1 deletion(-)
diff --git
This patch expose a public API virNodeCacheStats to query cache stats
on a host.
Signed-off-by: Eli Qiao <liyong.q...@intel.com>
---
daemon/remote.c| 67 ++
include/libvirt/libvirt-host.h | 32
src/driver-hyperv
to maintain resource control information.
Some of host cpu related information methods was added in virhostcpu.c
Signed-off-by: Eli Qiao <liyong.q...@intel.com>
---
include/libvirt/virterror.h | 1 +
po/POTFILES.in | 1 +
src/Makefile.am | 1 +
src/libvirt_privat
Signed-off-by: Eli Qiao <liyong.q...@intel.com>
---
src/conf/capabilities.c | 56 ++
src/conf/capabilities.h | 23
src/libvirt_private.syms | 3 +++
src/nodeinfo.c
Add new virsh command line `nodecachestats` to expose the cache usage
on a node.
Signed-off-by: Eli Qiao <liyong.q...@intel.com>
---
src/libvirt_private.syms | 3 ++-
src/qemu/qemu_driver.c | 12 ++
src/util/virresctrl.c| 62 +++
em fs.
There are still one TODO left:
2. Expose a new public interface to set cachetune lively.
Some discussion about this feature support can be found from:
https://www.redhat.com/archives/libvir-list/2017-January/msg00644.html
*** BLURB HERE ***
Eli Qiao (12):
Resctrl: Add some utils f
This patch adds new xml element to support cache tune as:
...
...
id: any non-minus number
host_id: reference of the host's cache banks id, it's from capabilities
type: cache bank type
size: should be multiples of the min_size of the bank on host.
vcpus: cache allocation on vcpu set, if
bank.
We need also to add lock to access /sys/fs/resctrl, use flock.
Signed-off-by: Eli Qiao <liyong.q...@intel.com>
---
src/util/virresctrl.c | 93 ---
src/util/virresctrl.h | 3 ++
2 files changed, 83 insertions(+), 13 deletions(-)
diff
While user can assign some specific vcpus list in , adds the
vcpus' pids to cache bank, else vm->pid will be added to cache bank.
Signed-off-by: Eli Qiao <liyong.q...@intel.com>
---
src/qemu/qemu_driver.c | 6 --
src/qemu/qemu_proce
Other application may touch resctrl while libvirt's running, scan
resctrl again before allocating cache information to the newly created
VM.
Signed-off-by: Eli Qiao <liyong.q...@intel.com>
---
src/util/virresctrl.c | 40
1 file changed, 40 inse
While user can assign some specific vcpus list in , adds the
vcpus' pids to cache bank, else vm->pid will be added to cache bank.
Signed-off-by: Eli Qiao <liyong.q...@intel.com>
---
src/qemu/qemu_driver.c | 6 --
src/qemu/qemu_proce
directory, and update the schemata
after libvirt domain destroy.
Signed-off-by: Eli Qiao <liyong.q...@intel.com>
---
src/libvirt_private.syms | 6 +-
src/util/virresctrl.c| 677 +++
src/util/virresctrl.h| 5 +-
3
Best regards
- Eli
天涯无处不重逢
a leaf duckweed belongs to the sea, where not to meet in life
2017-03-03 10:24 GMT+08:00 Marcelo Tosatti <mtosa...@redhat.com
(mailto:mtosa...@redhat.com)>:
> On Mon, Feb 27, 2017 at 03:22:56PM +0800, Eli Qiao wrote:
> > Add new vir
This patch expose a public API virNodeCacheStats to query cache stats
on a host.
Signed-off-by: Eli Qiao <liyong.q...@intel.com>
---
daemon/remote.c| 67 ++
include/libvirt/libvirt-host.h | 32
src/driver-hyperv
l3data and l3code type of cache banks should be configured pairs.
Signed-off-by: Eli Qiao <liyong.q...@intel.com>
---
src/conf/domain_conf.c | 19 +++
src/util/virresctrl.c | 1 -
src/util/virresctrl.h | 2 ++
3 files changed, 21 insertions(+), 1 deletion(-)
diff --git
resctrl -o cdp /sys/fs/resctrl
Signed-off-by: Eli Qiao <liyong.q...@intel.com>
---
docs/schemas/domaincommon.rng | 2 +-
src/util/virresctrl.c | 27 +--
2 files changed, 26 insertions(+), 3 deletions(-)
diff --git a/docs/schemas/domaincommon.rng b/docs/s
Add new virsh command line `nodecachestats` to expose the cache usage
on a node.
Signed-off-by: Eli Qiao <liyong.q...@intel.com>
---
src/libvirt_private.syms | 3 ++-
src/qemu/qemu_driver.c | 12 ++
src/util/virresctrl.c| 62 +++
to maintain resource control information.
Some of host cpu related information methods was added in virhostcpu.c
Signed-off-by: Eli Qiao <liyong.q...@intel.com>
---
include/libvirt/virterror.h | 1 +
po/POTFILES.in | 1 +
src/Makefile.am | 1 +
src/libvirt_privat
bank.
We need also to add lock to access /sys/fs/resctrl, use flock.
Signed-off-by: Eli Qiao <liyong.q...@intel.com>
---
src/util/virresctrl.c | 93 ---
src/util/virresctrl.h | 3 ++
2 files changed, 83 insertions(+), 13 deletions(-)
diff
Other application may touch resctrl while libvirt's running, scan
resctrl again before allocating cache information to the newly created
VM.
Signed-off-by: Eli Qiao <liyong.q...@intel.com>
---
src/util/virresctrl.c | 40
1 file changed, 40 inse
em fs.
There are still one TODO left:
1. Expose a new public interface to get free cache information.
2. Expose a new public interface to set cachetune lively.
Some discussion about this feature support can be found from:
https://www.redhat.com/archives/libvir-list/2017-January/msg00644
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