On Wed, Jan 06, 2021 at 21:59:21 +0100, Ján Tomko wrote:
> On a Wednesday in 2021, Peter Krempa wrote:
> > Objects such as domain, pool, etc re-define the regex for the format.
> > Add more generic types for objects with/without a slash which we'll be
> > able to reuse also for other objects.
> >
On a Thursday in 2021, Peter Krempa wrote:
On Wed, Jan 06, 2021 at 21:59:21 +0100, Ján Tomko wrote:
On a Wednesday in 2021, Peter Krempa wrote:
> Objects such as domain, pool, etc re-define the regex for the format.
> Add more generic types for objects with/without a slash which we'll be
> able
On Tue, Jan 05, 2021 at 15:12:55 +0100, Peter Krempa wrote:
> On Mon, Jan 04, 2021 at 15:30:19 -0500, Masayoshi Mizuma wrote:
> > On Sat, Dec 19, 2020 at 11:30:39PM -0500, Masayoshi Mizuma wrote:
[...]
> {"execute":"cont"}
>
> So that is a no-go. Some disk bus-es such as IDE don't support
On Thu, Jan 7, 2021 at 5:23 PM Peter Krempa wrote:
> Similarly to startup of the VM qemu doesn't like setting throttling for
> an empty drive. Just skip it since we do the correct thing once new
> media is inserted.
>
> Resolves: https://gitlab.com/libvirt/libvirt/-/issues/117
> Signed-off-by:
On 1/7/21 12:55 AM, Laine Stump wrote:
Laine Stump (2):
lxc: remove unnecessary call to virNetDevReserveName()
lxc: eliminate leaked and dangling pointers in
virLXCProcessSetupInterfaceTap
src/lxc/lxc_process.c | 13 ++---
1 file changed, 6 insertions(+), 7 deletions(-)
On 1/6/21 3:03 PM, Peter Krempa wrote:
This allows simplification of the callers.
Signed-off-by: Peter Krempa
---
src/qemu/qemu_migration_params.c | 13 -
src/qemu/qemu_monitor.c | 11 +++
src/qemu/qemu_monitor.h | 2 +-
src/qemu/qemu_monitor_json.c
On 1/6/21 3:03 PM, Peter Krempa wrote:
This allows simplification of the caller as well as will enable a later
refactor of qemuMonitorJSONMakeCommandInternal.
Signed-off-by: Peter Krempa
---
src/qemu/qemu_migration_params.c | 9 +++--
src/qemu/qemu_monitor.c | 11 +++
On 1/6/21 3:03 PM, Peter Krempa wrote:
Use automatic memory freeing and remove the 'cleanup' label and 'ret'
variable.
Signed-off-by: Peter Krempa
---
src/qemu/qemu_monitor_json.c | 24 +---
1 file changed, 9 insertions(+), 15 deletions(-)
diff --git
On 1/6/21 3:03 PM, Peter Krempa wrote:
This is a resend of the patches from:
https://www.redhat.com/archives/libvir-list/2020-November/msg01625.html
which can be justified without the rest of the series. This series
cleans up some monitor code and few related bits to testing.
The reset of the
On 12/18/20 1:56 AM, Nikolay Shirokovskiy wrote:
> Otherwise in some places we can mistakenly report 'unsupported' error instead
> of root cause. So let's handle root cause explicitly from the macro.
>
> Signed-off-by: Nikolay Shirokovskiy
> ---
> src/libvirt-domain.c | 511
>
On 1/7/21 12:51 AM, Laine Stump wrote:
virDeviceHasPCIExpressLink() wasn't checking that pcie_cap_pos was
valid before attempting to use it, which could lead to reading the
byte at offset 0+PCI_CAP_ID_EXP instead of [valid
offset]+PCI_CAP_ID_EXP. In particular, this could happen for
"integrated"
On a Thursday in 2021, Peter Krempa wrote:
See 2/2
Peter Krempa (2):
qemuDomainSetBlockIoTune: Remove old uninformative comment
qemuDomainSetBlockIoTune: Skip monitor call for empty cdrom
src/qemu/qemu_driver.c | 26 +++---
1 file changed, 15 insertions(+), 11 deletions(-)
On 1/7/21 12:53 PM, John Ferlan wrote:
On 12/18/20 1:56 AM, Nikolay Shirokovskiy wrote:
Otherwise in some places we can mistakenly report 'unsupported' error instead
of root cause. So let's handle root cause explicitly from the macro.
Signed-off-by: Nikolay Shirokovskiy
---
Signed-off-by: Peter Krempa
---
src/qemu/qemu_driver.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/src/qemu/qemu_driver.c b/src/qemu/qemu_driver.c
index 26c6e9b2e1..1283e61785 100644
--- a/src/qemu/qemu_driver.c
+++ b/src/qemu/qemu_driver.c
@@ -16301,9 +16301,6 @@
Similarly to startup of the VM qemu doesn't like setting throttling for
an empty drive. Just skip it since we do the correct thing once new
media is inserted.
Resolves: https://gitlab.com/libvirt/libvirt/-/issues/117
Signed-off-by: Peter Krempa
---
CC: Han Han
Please test this commit since you
See 2/2
Peter Krempa (2):
qemuDomainSetBlockIoTune: Remove old uninformative comment
qemuDomainSetBlockIoTune: Skip monitor call for empty cdrom
src/qemu/qemu_driver.c | 26 +++---
1 file changed, 15 insertions(+), 11 deletions(-)
--
2.29.2
On Wed, Jan 6, 2021 at 3:17 PM Luyao Zhong wrote:
> Reviewed-by: Daniel Henrique Barboza
> Signed-off-by: Luyao Zhong
> ---
> include/libvirt/libvirt-domain.h | 1 +
> src/conf/numa_conf.c | 9 +
> src/qemu/qemu_command.c | 6
On Mon, Jan 04, 2021 at 05:43:32PM +0100, Peter Krempa wrote:
> On Mon, Dec 14, 2020 at 16:55:33 +0100, Pavel Hrdina wrote:
> > Up until now we had a runtime code and XML related code in the same
> > source file inside util directory.
> >
> > This patch takes the runtime part and extracts it into
On Thu, Jan 07, 2021 at 14:17:04 +0100, Pavel Hrdina wrote:
> On Mon, Jan 04, 2021 at 05:43:32PM +0100, Peter Krempa wrote:
> > On Mon, Dec 14, 2020 at 16:55:33 +0100, Pavel Hrdina wrote:
[...]
> Thanks for the explanation for what the functions are used but it
> doesn't make it clear to me
The @fds member of qemuMonitorFdsetInfo struct is an array and as
such, it's allocated in qemuMonitorJSONQueryFdsetsParse() but not
freed in qemuMonitorFdsetsFree().
Fixes: b8998cc670f7b1b11a83276050e49dce7efba333
Signed-off-by: Michal Privoznik
---
src/qemu/qemu_monitor.c | 2 ++
1 file
On a Thursday in 2021, Laine Stump wrote:
On 1/7/21 10:09 AM, Michal Privoznik wrote:
When defining/creating a network the bridge name may be filled in
automatically by libvirt (if none provided in the input XML or
the one provided is a pattern, e.g. "virbr%d"). During the
bridge name
On a Thursday in 2021, Erik Skultety wrote:
We set the pointer to some garbage packed structure data without
knowing whether it actually we were handling the type of device we
expected to be handling. On its own, this was harmless, because we'd
never use the pointer as we'd skip the device if it
On a Thursday in 2021, Peter Krempa wrote:
See patch 3/5 for explanation.
Peter Krempa (5):
virDomainDiskDefFormatDriver: Rename 'driverBuf' to 'attrBuf'
virDomainSnapshotDiskDefFormat: Use virXMLFormatElement
conf: Introduce subelement of
conf: snapshot: Add support for
qemu: Implement
On a Thursday in 2021, Peter Krempa wrote:
In certain specific cases it might be beneficial to be able to control
the metadata caching of storage image format drivers of a hypervisor.
Introduce XML machinery to set the maximum size of the metadata cache
which will be used by qemu's qcow2
On 1/6/21 7:46 PM, Philippe Mathieu-Daudé wrote:
> The 'fulong2e' machine alias has been marked as deprecated since
> QEMU v5.1 (commit c3a09ff68dd, the machine is renamed 'fuloong2e').
> Time to remove it now.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> docs/system/deprecated.rst |
On Thu, Jan 7, 2021 at 12:38 PM Jiri Denemark wrote:
>
> On Thu, Jan 07, 2021 at 09:58:09 -0500, Neal Gompa wrote:
> > This is automatically picked up by the dependency generator, so
> > there's no reason to have this here.
> >
> > Signed-off-by: Neal Gompa
> > ---
> > libvirt.spec.in | 1 -
> >
On a Thursday in 2021, Erik Skultety wrote:
The lookup didn't do anything apart from comparing the sysfs paths
anyway since that's what makes each mdev unique.
The most ridiculous usage of the old logic was in
virHostdevReAttachMediatedDevices where in order to drop an mdev
hostdev from the list
On a Thursday in 2021, Peter Krempa wrote:
In certain specific cases it might be beneficial to be able to control
the metadata caching of storage image format drivers of a hypervisor.
Introduce XML machinery to set the maximum size of the metadata cache
which will be used by qemu's qcow2
On a Thursday in 2021, Peter Krempa wrote:
qemu's qcow2 driver allows control of the metadata cache of qcow2 driver
by the 'cache-size' property. Wire it up to the recently introduced
elements.
Signed-off-by: Peter Krempa
---
src/qemu/qemu_block.c | 11
The MIPS ISA release 5 is common to 32/64-bit CPUs.
To avoid holes in the insn_flags type, update the
definition with the next available bit.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210104221154.3127610-15-f4...@amsat.org>
---
The MIPS ISA release 6 is common to 32/64-bit CPUs.
To avoid holes in the insn_flags type, update the
definition with the next available bit.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210104221154.3127610-16-f4...@amsat.org>
---
target/mips/internal.h
The MIPS ISA release 2 is common to 32/64-bit CPUs.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210104221154.3127610-13-f4...@amsat.org>
---
target/mips/internal.h | 2 +-
target/mips/mips-defs.h| 4 +-
linux-user/mips/cpu_loop.c | 2 +-
Use the single ISA_MIPS32R5 definition to check if the Release 5
ISA is supported, whether the CPU support 32/64-bit.
For now we keep '32' in the definition name, we will rename it
as ISA_MIPS_R5 in few commits.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id:
Use the single ISA_MIPS32R6 definition to check if the Release 6
ISA is supported, whether the CPU support 32/64-bit.
For now we keep '32' in the definition name, we will rename it
as ISA_MIPS_R6 in few commits.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id:
The MIPS ISA release '1' is common to 32/64-bit CPUs.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210104221154.3127610-12-f4...@amsat.org>
---
target/mips/internal.h | 2 +-
target/mips/mips-defs.h | 4 +--
target/mips/translate.c | 54
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20201206233949.3783184-15-f4...@amsat.org>
---
target/mips/internal.h | 1 +
target/mips/tlb_helper.c | 46 ++
target/mips/translate_init.c.inc | 48
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20201214183739.500368-5-f4...@amsat.org>
---
target/mips/helper.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/target/mips/helper.c b/target/mips/helper.c
index 92bd3fb8550..cfb6d82fd33 100644
---
This file contains functions related to TLB management,
rename it as 'tlb_helper.c'.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20201206233949.3783184-13-f4...@amsat.org>
---
target/mips/{helper.c => tlb_helper.c} | 2 +-
target/mips/meson.build
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20201214183739.500368-2-f4...@amsat.org>
---
target/mips/cpu.c | 26 +-
1 file changed, 9 insertions(+), 17 deletions(-)
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index
To help understand ifdef'ry, add comment after #endif.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20201214183739.500368-4-f4...@amsat.org>
---
target/mips/helper.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git
We are going to move this code, fix its style first.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20201206233949.3783184-14-f4...@amsat.org>
---
target/mips/translate_init.c.inc | 36
1 file changed, 18 insertions(+), 18
Extract FPU specific helpers from "internal.h" to "fpu_helper.h".
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20201120210844.2625602-2-f4...@amsat.org>
---
target/mips/fpu_helper.h | 59
target/mips/internal.h
The MIPS ISA release 3 is common to 32/64-bit CPUs.
To avoid holes in the insn_flags type, update the
definition with the next available bit.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210104221154.3127610-14-f4...@amsat.org>
---
CACHE/PREF opcodes have been removed from the Release 6.
Add a single decodetree entry for the opcodes, triggering
Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() calls.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id:
Special2 opcode have been removed from the Release 6.
Add a single decodetree entry for all the opcode class,
triggering Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() call.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id:
Now that we can decode the MSA ASE with decode_ase_msa(),
use it and remove the previous code, now unreachable.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20201215225757.764263-21-f4...@amsat.org>
Tested-by: Jiaxun Yang
---
target/mips/translate.h |
Introduce the 'msa32' decodetree config for the 32-bit MSA ASE.
We start by decoding:
- the branch instructions,
- all instructions based on the MSA opcode.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20201215225757.764263-20-f4...@amsat.org>
Reviewed-by:
COP1x opcode has been removed from the Release 6.
Add a single decodetree entry for it, triggering
Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() call.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id:
LWL/LWR/SWL/SWR opcodes have been removed from the Release 6.
Add a single decodetree entry for the opcodes, triggering
Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() calls.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id:
LWLE/LWRE/SWLE/SWRE (EVA) opcodes have been removed from
the Release 6. Add a single decodetree entry for the opcodes,
triggering Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() calls.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
LDL/LDR/SDL/SDR opcodes have been removed from the Release 6.
Add a single decodetree entry for the opcodes, triggering
Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() calls.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id:
Add the LSA opcode to the MSA32 decodetree config, add DLSA
to a new config for the MSA64 ASE, and call decode_msa64()
in the main decode_opc() loop.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20201215225757.764263-23-f4...@amsat.org>
---
LSA and LDSA opcodes are also available with MIPS release 6.
Introduce the decodetree config files and call the decode()
helpers in the main decode_opc() loop.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20201215225757.764263-24-f4...@amsat.org>
---
Since we switched to decodetree-generated processing,
we can remove this now unreachable code.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20201208203704.243704-6-f4...@amsat.org>
---
target/mips/translate.c | 29 +
1 file
Extract gen_lsa() from translate.c and explode it as
gen_LSA() and gen_DLSA().
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20201215225757.764263-22-f4...@amsat.org>
---
target/mips/translate.h| 6 +++
target/mips/translate.c| 35
Simplify gen_check_zero_element() by passing the TCGCond
argument along.
Suggested-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20201215225757.764263-25-f4...@amsat.org>
---
target/mips/msa_translate.c | 10 --
1 file changed,
Use the single ISA_MIPS32R3 definition to check if the Release 3
ISA is supported, whether the CPU support 32/64-bit.
For now we keep '32' in the definition name, we will rename it
as ISA_MIPS_R3 in few commits.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id:
Use the single ISA_MIPS32 definition to check if the Release 1
ISA is supported, whether the CPU support 32/64-bit.
For now we keep '32' in the definition name, we will rename it
as ISA_MIPS_R1 in few commits.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id:
Use the single ISA_MIPS32R2 definition to check if the Release 2
ISA is supported, whether the CPU support 32/64-bit.
For now we keep '32' in the definition name, we will rename it
as ISA_MIPS_R2 in few commits.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id:
Directly check if the CPU supports 64-bit with the recently
added cpu_type_is_64bit() helper (inlined).
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20210104221154.3127610-6-f4...@amsat.org>
---
hw/mips/boston.c | 6 ++
1 file changed, 2 insertions(+),
The following changes since commit 470dd6bd360782f5137f7e3376af6a44658eb1d3:
Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-060121-4'
into staging (2021-01-06 22:18:36 +)
are available in the Git repository at:
https://gitlab.com/philmd/qemu.git tags/mips-20210107
From: Jiaxun Yang
It's useful for bootloader to do I/O operations.
Signed-off-by: Jiaxun Yang
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Huacai Chen
Message-Id: <20201215064507.30148-3-jiaxun.y...@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé
The MIPS3 and MIPS32/64 ISA use different definitions
for the CP0 Config0 register.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20201201132817.2863301-2-f4...@amsat.org>
---
target/mips/cpu.h | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
Move CPU_MIPS5 after CPU_MIPS4 :)
Reviewed-by: Jiaxun Yang
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210104221154.3127610-3-f4...@amsat.org>
---
target/mips/mips-defs.h | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git
'CPU_MIPS32' and 'CPU_MIPS64' definitions concern CPUs implementing
the "Release 1" ISA. Rename it with the 'R1' suffix, as the other
CPU definitions do.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20210104221154.3127610-4-f4...@amsat.org>
---
MIPS 64-bit ISA is introduced with MIPS3.
Introduce the CPU_MIPS64 definition aliased to the MIPS3 ISA,
and the cpu_type_is_64bit() method to check if a CPU supports
this ISA (thus is 64-bit).
Suggested-by: Jiaxun Yang
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20201201132817.2863301-3-f4...@amsat.org>
---
target/mips/translate_init.c.inc | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/target/mips/translate_init.c.inc
Remove a comment added 12 years ago but never used (commit
b6d96beda3a: "Use temporary registers for the MIPS FPU emulation").
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20210104221154.3127610-2-f4...@amsat.org>
---
target/mips/mips-defs.h | 6 --
1
Keep all MSA-related code altogether.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20201120210844.2625602-4-f4...@amsat.org>
Tested-by: Jiaxun Yang
---
target/mips/helper.h | 436 +-
target/mips/msa_helper.h.inc |
Make gen_msa() and gen_msa_branch() public declarations
so we can keep calling them once extracted from the big
translate.c in the next commit.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20201215225757.764263-18-f4...@amsat.org>
Tested-by: Jiaxun Yang
---
In preparation of using the decodetree script, explode
gen_msa_branch() as following:
- OPC_BZ_V -> BxZ_V(EQ)
- OPC_BNZ_V -> BxZ_V(NE)
- OPC_BZ_[BHWD] -> BxZ(false)
- OPC_BNZ_[BHWD]-> BxZ(true)
Reviewed-by: Jiaxun Yang
Reviewed-by: Richard Henderson
translate_init.c.inc mostly contains CPU definitions.
msa_reset() doesn't belong here, move it with the MSA
helpers.
One comment style is updated to avoid checkpatch.pl warning.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id:
We have ~400 lines of MSA helpers in the generic op_helper.c,
move them with the other helpers in 'msa_helper.c'.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20201123204448.3260804-5-f4...@amsat.org>
Tested-by: Jiaxun Yang
---
target/mips/msa_helper.c |
We don't use ASE_MSA anymore (replaced by ase_msa_available()
checking MSAP bit from CP0_Config3). Remove it.
Reviewed-by: Jiaxun Yang
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Tested-by: Jiaxun Yang
Message-Id: <20201208003702.4088927-6-f4...@amsat.org>
---
The msa_wr_d[] registers are only initialized/used by MSA.
They are declared static. We want to move them to the new
'msa_translate.c' unit in few commits, without having to
declare them global (with extern).
Extract first the logic initialization of the MSA registers
from the generic
The gen_msa*() methods don't use the "CPUMIPSState *env"
argument. Remove it to simplify.
Reviewed-by: Jiaxun Yang
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Tested-by: Jiaxun Yang
Message-Id: <20201208003702.4088927-9-f4...@amsat.org>
---
target/mips/translate.c |
Only decode MSA opcodes if MSA is present (implemented).
Now than check_msa_access() will only be called if MSA is
present, the only way to have MIPS_HFLAG_MSA unset is if
MSA is disabled (bit CP0C5_MSAEn cleared, see previous
commit). Therefore we can remove the 'reserved instruction'
exception.
Commits 863f264d10f ("add msa_reset(), global msa register") and
cb269f273fd ("fix multiple TCG registers covering same data")
removed the FPU scalar registers and replaced them by aliases to
the MSA vector registers.
It is not very clear to have FPU registers displayed with MSA
register names,
LLD/SCD opcodes have been removed from the Release 6.
Add a single decodetree entry for the opcodes, triggering
Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() calls.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id:
LL/SC opcodes have been removed from the Release 6.
Add a single decodetree entry for the opcodes, triggering
Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() calls.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id:
The 'fulong2e' machine alias has been marked as deprecated since
QEMU v5.1 (commit c3a09ff68dd, the machine is renamed 'fuloong2e').
Time to remove it now.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Huacai Chen
Reviewed-by: Thomas Huth
Message-Id:
On 1/7/21 5:22 PM, Ján Tomko wrote:
On a Thursday in 2021, Laine Stump wrote:
On 1/7/21 10:09 AM, Michal Privoznik wrote:
When defining/creating a network the bridge name may be filled in
automatically by libvirt (if none provided in the input XML or
the one provided is a pattern, e.g.
the Git repository at:
>
> https://gitlab.com/philmd/qemu.git tags/mips-20210107
>
> for you to fetch changes up to f97d339d612b86d8d336a11f01719a10893d6707:
>
> docs/system: Remove deprecated 'fulong2e' machine
On Wed, Jan 06, 2021 at 11:05:11 +0100, Tim Wiederhake wrote:
> Signed-off-by: Tim Wiederhake
> ---
> src/cpu_map/index.xml | 1 +
> src/cpu_map/meson.build | 1 +
> src/cpu_map/x86_Snowridge.xml | 71 +++
>
On Wed, Jan 06, 2021 at 11:05:07 +0100, Tim Wiederhake wrote:
> Signed-off-by: Tim Wiederhake
> ---
> src/cpu_map/x86_features.xml | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/src/cpu_map/x86_features.xml b/src/cpu_map/x86_features.xml
> index b0bf22d916..a5a987deba 100644
> ---
On Wed, Jan 06, 2021 at 11:05:04 +0100, Tim Wiederhake wrote:
> This series adds and enables the Snowridge CPU model.
>
> Note that qemu currently uses the same model ID for Icelake-Server [1]
> and Snowridge [2]. The correct ID for Icelake is 106 [3], a mistake
> that has been fixed in libvirt
Signed-off-by: Jiri Denemark
---
tests/cputestdata/cpu-gather.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/cputestdata/cpu-gather.py b/tests/cputestdata/cpu-gather.py
index f679fb9066..b8c1f23c82 100755
--- a/tests/cputestdata/cpu-gather.py
+++
Jiri Denemark (3):
cpu-gather: Remove redundant "processor" from CPU data file names
cpu_map: Suggest better command for updating test data files
cpu-gather: Rename the script as cpu-data.py
src/cpu_map/x86_features.xml | 5 ++---
tests/cputestdata/{cpu-gather.py =>
cpu-cpuid.py was merged into cpu-gather.py and the script can handle
multiple files so there's no need for a loop around it.
Signed-off-by: Jiri Denemark
---
src/cpu_map/x86_features.xml | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/src/cpu_map/x86_features.xml
It is now doing way more than gathering the CPU data from a host as the
other scripts were merged in it.
Signed-off-by: Jiri Denemark
---
src/cpu_map/x86_features.xml | 2 +-
tests/cputestdata/{cpu-gather.py => cpu-data.py} | 2 +-
2 files changed, 2 insertions(+), 2
Patchew URL: https://patchew.org/QEMU/2021010753.20382-1-f4...@amsat.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 2021010753.20382-1-f4...@amsat.org
Subject: [PULL 00/66] MIPS patches for 2021-01-07
===
On Thu, Jan 07, 2021 at 09:05:42AM +0100, Peter Krempa wrote:
> On Tue, Jan 05, 2021 at 15:12:55 +0100, Peter Krempa wrote:
> > On Mon, Jan 04, 2021 at 15:30:19 -0500, Masayoshi Mizuma wrote:
> > > On Sat, Dec 19, 2020 at 11:30:39PM -0500, Masayoshi Mizuma wrote:
>
> [...]
>
> >
gen_reserved_instruction() is easier to read than
generate_exception_end(ctx, EXCP_RI), replace it.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20201214183739.500368-12-f4...@amsat.org>
---
target/mips/translate.h | 1 +
target/mips/translate.c | 729
Some FPU translation functions / registers can be used by
ISA / ASE / extensions out of the big translate.c file.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20201214183739.500368-15-f4...@amsat.org>
---
target/mips/translate.h | 7 +++
Extract FPU specific definitions that can be used by
ISA / ASE / extensions to translate.h header.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20201214183739.500368-16-f4...@amsat.org>
---
target/mips/translate.h | 71
The rest of helper.c is TLB related. Extract the non TLB
specific functions to cpu.c, so we can rename helper.c as
tlb_helper.c in the next commit.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20201214183739.500368-6-f4...@amsat.org>
---
This file is not TCG specific, contains CPU definitions
and is consumed by cpu.c. Rename it as such.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20201214183739.500368-10-f4...@amsat.org>
---
target/mips/cpu.c| 2 +-
Extract DisasContext to a new 'translate.h' header so
different translation files (ISA, ASE, extensions)
can use it.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20201207235539.4070364-2-f4...@amsat.org>
---
target/mips/translate.h | 50
MSA presence is expressed by the MSAP bit of CP0_Config3.
We don't need to check anything else.
Reviewed-by: Jiaxun Yang
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Tested-by: Jiaxun Yang
Message-Id: <20201208003702.4088927-4-f4...@amsat.org>
---
Some CPU translation functions / registers / macros and
definitions can be used by ISA / ASE / extensions out of
the big translate.c file. Declare them in "translate.h".
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20201207235539.4070364-3-f4...@amsat.org>
1 - 100 of 149 matches
Mail list logo
