These assembler implementations of SHA1 and AES have been
in the upstream source tree since September 2012 but need
to be selected explicitly in order to be enabled.
Signed-off-by: Ard Biesheuvel
---
linaro/configs/linaro-base.conf | 2 ++
1 file changed, 2 insertions(+)
diff --git a/linaro
On 14 May 2013 18:49, Jon Medhurst (Tixy) wrote:
>
> This also enables CONFIG_CRYPTO_SHA1 which we didn't already have
> enabled in our builds, so I assume nothing actually needs this option.
> If that's true, then it doesn't seem worth enabling an optimised version
> of code which isn't going to
t (Tixy)
> wrote:
>>
>> On Tue, 2013-05-14 at 14:16 +0200, Ard Biesheuvel wrote:
>> > These assembler implementations of SHA1 and AES have been
>> > in the upstream source tree since September 2012 but need
>> > to be selected explicitly in order to be en
On 15 May 2013 14:05, Jon Medhurst (Tixy) wrote:
> If the assembler version is always faster I would have thought that we
> should always have it enabled and not have it as a user visible option.
> Perhaps the fact that the assembler is specifically target at ARMv4
> means that on ARMv7 CPUs the l
On 15 May 2013 14:38, Jon Medhurst (Tixy) wrote:
> I see that the ARM version is following the pattern of SPARC64 and X86
> SSSE3 in how it is configured, so for fear of opening a can of worms,
> perhaps it's simpler if we just go with the linaro-base.conf patch which
> started this thread? :-)
>
On 7 October 2013 11:30, Matthew Gretton-Dann
wrote:
> On 7 October 2013 05:20, Keith Packard wrote:
[...]
>> 2) The thumb version of libgcc.a is not built with thumb instructions
>> because GCC doesn't pass -mthumb to the assembler when it receives
>> -mthumb on the command line.
>
>
This adds support for the AESE/AESD/AESMC/AESIMC instructions that
are available on some v8 implementations of Aarch32.
Signed-off-by: Ard Biesheuvel
---
target-arm/Makefile.objs | 1 +
target-arm/crypto_helper.c | 196 +
target-arm/helper.h
On 6 November 2013 13:51, Peter Maydell wrote:
> On 6 November 2013 11:22, Ard Biesheuvel wrote:
>> This adds support for the AESE/AESD/AESMC/AESIMC instructions that
>> are available on some v8 implementations of Aarch32.
>
> Thanks for this patch. Please could you send Q
On 6 November 2013 14:21, Peter Maydell wrote:
> On 6 November 2013 13:05, Ard Biesheuvel wrote:
[...]
>> Thanks, I was wondering about that. Should there be another check? Not
>> all v8 cores will implement these extensions, so we might also want to
>> emulate one th
On 13 November 2013 07:41, Anil Singhar wrote:
> Thanks for your response. Here is the error I get when I do the "make check"
> step on the foundation model after having done the "configure" and "make"
> steps on the x86_64 linux build machine. I used the configure options you
> provided.
>
> 1.
On 13 November 2013 14:48, Matthew Gretton-Dann
wrote:
> On 13 November 2013 10:02, Zhenqiang Chen wrote:
>>> From: Deepak Saxena
>>> Date: 12 November 2013 07:25
>>> Subject: Running Linaro toolchain on ubuntu 13.10 x86_64
>>> To: Linaro Dev
>>>
>>>
>>> I'm working on getting my new build syst
On 30 January 2014 04:50, Anil Singhar wrote:
> Does anyone know how to increase the disk size on Foundation Model?
>
> For some reason, the network connectivity to the foundation model (via ssh
> localhost) doesn't work reliably. So my earlier attempts to mount my host
> computer's drive and get
On 30 January 2014 13:40, Anil Singhar wrote:
> Hi Ard,
>
> Thanks for your reply.
>
> I want to expand the available disk space inside the foundation model, so
> may be the second option you provided will accomplish that. Is that right?
> Currently the default is 8GB.
>
The second option implies
On 4 July 2014 18:13, Edward Nevill wrote:
> Hi,
>
> Does anyone know of a nice way to detect 64 x 64 -> 64 multiply overflow on
> aarch64?
>
> On x86 you can just use the V flag, but aarch64 seems to have no option to
> set the flags after a MUL instruction which I find very odd.
>
> The only s
On 29 August 2014 13:02, Edward Nevill wrote:
> We have a need on OpenJDK to flush the entire icache. Basically this
> need occurs when we do a garbage collection which may include garbage
> collection and patching of the dynamically generated code.
>
Surely, you could restrict the icache flush t
On 23 January 2015 at 16:28, Steve Capper wrote:
> Hi Yazen,
>
> This is looking good, just a few minor comments below.
>
> Cheers,
> --
> Steve
>
> On Fri, Jan 23, 2015 at 09:13:42AM -0600, Yazen Ghannam wrote:
>> ARMv8 defines a set of optional CRC32/CRC32C instructions.
>> This patch defines an
On 12 November 2015 at 06:43, Shawn Guo wrote:
> Hi,
>
> I need some help to understand aarch64-linux-gnu-objdump output in .data
> section as below. It's part of the dump of u-boot image with command
> 'aarch64-linux-gnu-objdump -D -z u-boot'.
>
> Disassembly of section .data:
>
> 350398
On 7 December 2015 at 11:51, Edward Nevill wrote:
> Hi,
>
> Does anyone know how I do
>
> adrp x0, dest & ~0xfff
> add x0, x0, dest & 0xfff
>
> in aarch64 assembler?
>
You can't. ADRP is PC relative, but rounded to page granularity, so
you can't use it for arbitrary expressions against
On 7 December 2015 at 14:40, Ard Biesheuvel wrote:
> On 7 December 2015 at 11:51, Edward Nevill wrote:
>> Hi,
>>
>> Does anyone know how I do
>>
>> adrp x0, dest & ~0xfff
>> add x0, x0, dest & 0xfff
>>
>> in aarch64 assembler?
On 7 December 2015 at 14:53, Edward Nevill wrote:
>> adrp, x0, dest
>> add x0, x0, #:lo12:dest
>
> Thanks! Thats the syntax I wanted.
>
> The use case is I want to benchmark this as a way of generating far
> calls, for use within the JIT for when code cache becomes > 128m.
>
> At the moment we gen
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