Hi Linaro Toolchain Group,
I have a question on the ldr instruction selection in the aarch64 backend.
Could someone help me in this regards, please?
I am trying to allow only type A instructions while disabling the type B.
Type A example: ldr x4, [x20,x1]---> allow
Type B example: ldr
aarch64_legitimate_address_hook_p is the place where the result of
aarch64_classify_address is returned to the middle-end. The middle-end then
knows that possibility for a+b is a legitimate address so it forces x3 << 3
into a register and tries aarch64_legitimate_address_hook_p again.
* Off from Mon. to Wed. [6/10]
# Progress #
* TCWG-518. Support range stepping on arm-linux. Ongoing. [2/10]
First do software single step in GDBserver side.
* TCWG-509. GDB 7.11 release. [1/10]
PR 19474, review Keith's patch. The patch is OK to mainline, but we
don't want to take
== Progress ==
* Conferences (4/10)
- Fosdem organisation, travel, video cutting (all lost)
- EuroLLVM paper review, schedule, meetings
* Buildbots (2/10)
- Bisecting test-suite regression
- Infrastructure clean up
- Reverting broken patches
* Support (1/10)
- Looking at some bugs, fixed
== Progress ==
* Validation
- disabled Auto Backport Engine until the patch selection
is improved to avoid saturating the builders with undesirable
builds.
- AArch64 bare metal validation (bug #2011). Submitted a patch
for dejagnu aarch64-fv8.exp, and one for our builders schroots.
