== Progress ==
* Remove exit-on-error flag from CodeGen tests [TCWG-604] [4/10]
- This is a follow-up of TCWG-592: when changing the diag handler,
some of the tests started to fail, so we had to add an exit-on-error
flag to preserve the old behaviour until we can fix the tests.
- Patch fixing
== Progress ==
* Remove exit-on-error flag from CodeGen tests [TCWG-604] [4/10]
- This is a follow-up of TCWG-592: when changing the diag handler,
some of the tests started to fail, so we had to add an exit-on-error
flag to preserve the old behaviour until we can fix the tests.
- Patch fixing
== Progress==
* Remove exit-on-error flag from CodeGen tests [TCWG-604] [5/10]
- This is a follow-up of TCWG-592: when changing the diag handler,
some of the tests started to fail, so we had to add an exit-on-error
flag to preserve the old behaviour until we can fix the tests.
- Last week's
== Progress ==
* Out of office on Monday [2/10]
* Remove exit-on-error flag from CodeGen tests [TCWG-604] [1/10]
- This is a follow-up of TCWG-592: when changing the diag handler,
some of the tests started to fail, so we had to add an exit-on-error
flag to preserve the old behaviour until we
== Progress ==
* Out of office on Monday and Tuesday [4/10]
* ARM: Do not test for CPUs, use SubtargetFeatures [TCWG-623] [4/10]
- First patch committed upstream (6 features / properties)
- Another patch in upstream review (5 features / properties)
- Working on another series of patches
*
== Progress ==
* Rework LLVM helper scripts [TCWG-571] [4/10]
- Code review + minor improvements to the scripts
- Started a discussion about the interfaces of some of the scripts
(llvm-projs, llvm-sync)
* Inline assembly constraints support for ARM [TCWG-560] [3/10]
- More investigations
== Progress ==
* Add a diag handler for llc so it doesn't exit on the first error it
finds [TCWG-592] [1/10]
- Fixed and rebased the patch, it has been committed upstream
* Inline assembly constraints support for ARM [TCWG-560] [1/10]
- Rebased the patch, it has been committed upstream
*
== Progress ==
* Add a diag handler for llc so it doesn't exit on the first error it
finds [TCWG-592] [5/10]
- Started a discussion about a new diagnostic handler for llc
- Patch accepted upstream, but broke a few things (Renato has
investigated/fixed some of them - thanks)
* Inline assembly
== Progress ==
* 3 days off (Mon/Thu/Fri) [6/10]
* Inline assembly constraints support for ARM [TCWG-560] [3/10]
- More investigations for PR24071; found the cause of the bug,
working on a fix.
* Rework LLVM helper scripts [TCWG-571] [1/10]
- Addressed code review comments.
- The
== Progress ==
* Refactor SelectionDAGBuilder::visitInlineAsm [TCWG-643] [1/10]
- Incorporated some review feedback and committed the patch upstream
* [AArch64] Support for label arithmetic in the assembler [TCWG-710] [4/10]
- Most of the support seems to be there, but the error checking is
== Progress ==
* ARM: Do not test for CPUs, use SubtargetFeatures [TCWG-623]
- Committed all 3 patches upstream
* ARM: Different ABI functions based on optimization level [TCWG-669]
- Patch in upstream review, had to rework it a bit
* PR26038 - inline assembly assertion building ARM linux
== Progress ==
* LLVM 3.9.0 Release for AArch64 [TCWG-696] [3/10]
- Ran the tests on one of our APM boards
- Fixed an issue with some tests that are only supposed to be run
for the x86 target but were accidentally running for other targets too
- Wrote up some release notes for AArch64
== Progress ==
* PR24234 - [AArch64] error in backend: fixup value out of range
[TCWG-681] [5/10]
- Wrong instruction size computed for TLS accesses
- Accepted upstream, will commit first thing next week
* [AArch64] Register all AArch64 passes [TCWG-687] [3/10]
- Cleanup that should enable
== Progress ==
* National holiday on Tuesday [2/10]
* [AArch64] Investigate PR30225 [TCWG-1021] [2/10]
- This was a bug related to the code alignment factor for the debug frame
- Decided it was not a correctness issue and the size savings for
using a different factor are probably not
== Progress ==
* [ARM GlobalISel] Fix atomic loads/stores after r294993 [TCWG-1041] [1/10]
- For the moment we just bail out if we have any atomic loads /
stores. This is better than silently replacing them with non-atomic
operations.
* [ARM GlobalISel] Add support for lowering calls
== Progress ==
* [ARM GlobalISel] Add support for fp arguments [TCWG-1029] [7/10]
- Committed support for double precision hard float and soft-fp
* [ARM GlobalISel] Fix atomic loads/stores after r294993 [TCWG-1041] [1/10]
- Worked on a patch that I'll probably commit next week
* Misc [2/10]
== Progress ==
* [ARM GlobalISel] Add support for fp arguments [TCWG-1029] [5/10]
- Committed support for single precision hard float and soft-fp ABIs
- Work in progress on supporting double precision
* Misc [5/10]
- Meetings, mailing lists, code reviews
- Reverted / fixed a few patches
== Progress ==
* Out of office Mon-Wed [6/10]
* [ARM] Use AddDefaultPred everywhere [TCWG-987]
- Committed upstream
* LLVM AArch64 4.0.0 [ TCWG-1008] [1/10]
- Ran the tests for rc1, everything went smoothly
* [AArch64] Investigate PR30225 [TCWG-1021] [1/10]
- Someone noticed that llvm-mc
== Progress ==
* LLVM 3.9.0 Release for AArch64 [TCWG-696] [1/10]
- Ran the tests for RC2, everything looks good on AArch64
* [AArch64] Support for label arithmetic in the assembler [TCWG-710] [3/10]
- This is starting to look like a patch, but I need to add more tests
* Buildbot
== Progress ==
* [Lab] ASAN test fails with glibc 2.23 [TCWG-811]
- Recommitted upstream after discussing with Adhemerval at Connect
(thanks, Adhemerval)
- The bot is now upstream
* Add worktree module to tcwg-release-tools [TCWG-783]
- In review. Trying to use it in our llvm-projs helper
== Progress ==
* [AArch64] Support for label arithmetic in the assembler [TCWG-710]
- 2 patches in upstream review
* Handle special cases in AArch64InstrInfo::GetInstSizeInBytes [TCWG-757]
- Committed a patch for stackmap / patchpoint sizes
- Since this was a bit cumbersome to test
== Progress ==
* [Lab] ASAN test fails with glibc 2.23 [TCWG-811] [4/10]
- This issue is keeping us from moving one of the TK1 bots into production
- Committed a patch upstream, but it broke on an x86_64 bot when
compiling with -m32
- I tracked the problem to the wrong glibc function being
== Progress ==
* [AArch64] Support for label arithmetic in the assembler [TCWG-710] [9/10]
- Patch in upstream review
- While adding more tests for the patch above, I noticed that we're not
encoding the lsl #12 on add/sub immediates correctly
- Submitted a patch to fix that as well
*
== Progress ==
* [ARM GlobalISel] Use CC support for lowering args/return [TCWG-946] [5/10]
- Sent a patch upstream for extracting some target-independent
functionality from the AArch64 GlobalISel
- Working on lowering i32 args for non-vararg functions (most of the
functionality is ready,
== Progress ==
* Rewrite llvm-projs in Python [TCWG-833] [2/10]
- Reorganized the repo and sent a draft for review to get early feedback
* [ARM GlobalISel] Select add instructions [TCWG-925] [3/10]
- Patch in upstream review
* [ARM GlobalISel] Use CC support for lowering args/return
== Progress ==
* Rewrite llvm-projs in Python [TCWG-833] [2/10]
- Investigated clitest for testing the scripts
- It seems to be a bit unwieldy for our purposes, so in the end it's
probably a better idea to abuse Python's unittest module even for higher
level tests (they'll be in a different
== Progress ==
* [ARM] Investigate switching from itineraries to schedule models
[TCWG-824] [4/10]
- Looked at the sched model as well as the old instruction itinerary
interfaces
- There aren't many tests that are specifically testing the scheduler,
but lots of tests break if you make enough
== Progress ==
* Test GlobalISel on AArch64 Linux [TCWG-825]
- Got the existing tests to work on Linux - luckily this only required
changes to the tests and not to GlobalISel itself; committed these changes
upstream
- Ran the test-suite with GlobalISel and with the fallback to the old DAG
== Progress ==
* [ARM GlobalISel] Use CC support for lowering args/return [TCWG-946] [2/10]
- Committed patch extracting target-independent functionality from
AArch64 GlobalISel
- Submitted patch using that functionality to lower any number of
i32 arguments
- Refactored [ARM GlobalISel]
== Progress ==
* [ARM GlobalISel] Add support for integers < 32 bits wide [TCWG-980] [4/10]
- A number of patches in upstream review
* [ARM] Refactor AddrMode3 [TCWG-989] [1/10]
- Did some preliminary investigations / tinkering for removing a
hack in the representation of LDRH
* Rewrite
== Progress ==
* [ARM] Use AddDefaultPred everywhere [TCWG-987] [1/10]
- Proposed a refactoring first [TCWG-1015]
- Rebased initial patch after the refactoring, still waiting for review
* Refactor AddDefaultPred [TCWG-1015] [4/10]
- Initial implementation was a bit heavyweight, so I worked
== Progress ==
* Out of office [2/10]
* [ARM GlobalISel] Use CC support for lowering args/return [TCWG-946] [1/10]
- Brushed up and committed upstream
* [ARM] Use AddDefaultPred everywhere [TCWG-987] [3/10]
- Patches in upstream review
* Misc [4/10]
- Mailing lists, meetings, 2017
== Progress ==
* [ARM GlobalISel] Use TableGen for inst selector [TCWG-1037] [3/10]
- Got some patches ready but they depend on the TableGen support for
predicates, which has not been committed upstream yet
* [GlobalISel] Use proper calling conv for calls [TCWG-1051] [1/10]
- Patch accepted
== Progress ==
* Out of office on Monday [2/10]
* [ARM GlobalISel] Investigate divmod [TCWG-1086]
- Broke this up into several smaller stories
* [ARM GlobalISel] Support sub and mul [TCWG-1104] [1/10]
- Committed upstream
* [ARM GlobalISel] Support trunc [TCWG-1109] [1/10]
- Committed
== Progress ==
* Out of office on Friday [2/10]
* [ARM GlobalISel] Add support for soft float targets [TCWG-1039] [2/10]
- Committed G_FPOW and G_FADD upstream
- Most of the other soft float libcalls are just a matter of boilerplate
* [GlobalISel] Investigate divmod [TCWG-1086] [5/10]
-
== Progress ==
* 2 days out of office (Thursday & Friday)
* [ARM GlobalISel] Add support for lowering calls [TCWG-1038]
- Committed support for GEPs and 32-bit constants, which enables us
to put call parameters on the stack
- Proposed a fix for an AArch64 issue where the size of the stack
== Progress ==
* [GlobalISel] AArch64 test-suite and self-host [TCWG-1074][3/10]
- Ran more tests and reported the results upstream
* [ARM GlobalISel] Add support for soft float targets [TCWG-1039][3/10]
- Started supporting G_FREM and G_FPOW, which are already handled by
the
== Progress ==
* TCWG-1155 - Move ASAN 39bit bot to GlobalISel [1/10]
- The bot is finally upstream and working well
* TCWG-1172 - [ARM GlobalISel] Support G_FCMP for s32 [7/10]
- Committed support for 32-bit floating point compares, both
hardware and software
* TCWG-1141 - Add "push"
== Progress ==
* TCWG-1187 - [ARM GlobalISel] Support G_FCMP for s64 [5/10]
- Committed upstream
- Also refactored the existing code a bit
* TCWG-1190 - [ARM GlobalISel] Support G_BR and G_BRCOND [2/10]
- Committed upstream
* TCWG-1191 - Test zorg patch [1/10]
- Test a patch for running
== Progress ==
* [ARM GlobalISel] Support globals [6/10]
- This is going to be very hairy because of all the different
relocation models (PIC, ROPI etc), differences between ELF and MachO,
and differences between targets with MOVT or without it
- Started adding support for simple, statically
== Progress ==
* TCWG-1155 - Move ASAN 39bit bot to GlobalISel [1/10]
- Moved to the public silent master, ready for the final move on
Monday if it's stable until then
* TCWG-1172 - [ARM GlobalISel] Support G_FCMP [5/10]
- Most of the functionality is implemented, but I intend to do a lot
of
== Progress ==
* [ARM GlobalISel] Support div [TCWG-1103] [1/10]
- Committed upstream
* [ARM GlobalISel] Fix fallback path [TCWG-1110] [2/10]
- Fixed and committed another issue
* [ARM GlobalISel] Fix loading i<32 from the stack [TCWG-1065] [2/10]
- Committed upstream
* Remove
== Progress ==
* Remove environment variables [TCWG-1114] [1/10]
- Committed
* [ARM GlobalISel] TableGen ISel for ADD/SUB [TCWG-1119] [5/10]
- Committed a change to the legalizer so that we widen narrow
operations (since we only have patterns for the 32-bit versions)
- Committed support
== Progress ==
* Out of office on Friday [2/10]
* TCWG-1155 - Move ASAN 39bit bot to GlobalISel [1/10]
- Committed a quick fix and started seeing green builds on this, we
can probably move it upstream soon
* TCWG-836 - Replace D01s by Scaleway boards [2/10]
- Set up a selfhost buildbot on
== Progress ==
* Bank holiday on Thursday [2/10]
* [ARM GlobalISel] Add support for struct / array args [TCWG-1033] [5/10]
- The array stuff is ready to commit, but SVN was down this morning
so I'll commit next week
* [GlobalISel] Run precommit for Daniel's patch [TCWG-1142] [2/10]
- Ran
== Progress ==
* [ARM GlobalISel] TableGen ISel for ADD/SUB [TCWG-1119] [1/10]
- Committed upstream
* [GlobalISel] AArch64 test-suite and self-host [TCWG-1074] [3/10]
- Found that we can't self-host anymore with GlobalISel, we get a
segfault in one of the tests
- After investigations it
== Progress ==
* [GlobalISel] AArch64 test-suite and self-host [TCWG-1074] [3/10]
- Reported and investigated a codegen issue introduced by one of
Quentin's patches, which was appearing while selfhosting with GlobalISel
- Ran the test-suite and self-host again after it was fixed
* [ARM
== Progress ==
* TCWG-1172 - [ARM GlobalISel] Support G_FCMP [2/10]
- In progress
* TCWG-1168 - [ARM GlobalISel] Support G_ICMP [3/10]
- Done, going to commit upstream
* TCWG-1136 - LLVM 4.0.1 [1/10]
- Spinned up rc3
* TCWG-1155 - Move ASAN 39bit bot to GlobalISel [2/10]
-
== Progress ==
* [ARM GlobalISel] Support AND, OR, XOR [TCWG-1157] [2/10]
- Committed upstream
* [ARM GlobalISel] Fix arm-irtranslator test [TCWG-1146] [1/10]
- Committed upstream
* [GlobalISel] Remove the G_SEQUENCE node [TCWG-1138] [1/10]
- Removed the G_SEQUENCE node from the ARM
== Progress ==
* Catch up on things
- Remind myself what a laptop looks like, install updates etc etc
- Figure out new links, machines etc
- Clean up inbox
* [LLVM-59] Small changes to the LLVM helper scripts
- Had a look at all the remaining issues and closed them as obsolete
or already
== Progress ==
* [ARM GlobalISel] Select complicated G_CONSTANT [LLVM-491]
- Committed upstream
* [ARM & Thumb GlobalISel] Support calls to vararg functions [LLVM-490]
- This gets rid of all the fallbacks in the test-suite related to
calls to printf (which is a lot)
- Committed upstream
*
== Progress ==
# [LLVM-492] [Thumb GlobalISel] Lower parameters for Thumb functions
- Committed upstream
# [LLVM-500] [Thumb GlobalISel] Support G_ADD, G_SUB, G_MUL
- Started working on this but it became apparent that the existing
tests would be easier to reuse if we had support for G_LOAD
== Progress ==
# Monday off
# [LLVM-479] Check current status of GlobalISel
- Looked into new patterns that can be selected by TableGen and
forked LLVM-481 and LLVM-482 out of that
- Ran a test-suite and a selfhost with GlobalISel and had a look at
the fallbacks
# [LLVM-481] [ARM
== Progress ==
* [ARM GlobalISel] Select complicated G_CONSTANT [LLVM-491]
- Negative constants in particular cause a lot of fallbacks in the
test-suite/selfhost
- Need to help TableGen produce code for MOVi32imm
- Ready to commit next week
- Looked a bit into enabling MVNi as well, but
== Progress ==
* LLVM 7.1.0 Release for ARM & AArch64 [LLVM-546]
- Uploaded RC1 for both ARM & AArch64
* [GlobalISel] Support debug info [LLVM-549]
- Added support for DBG_VALUE, seems to be enough for now
* [GlobalISel] Map and select G_FCONSTANT [LLVM-552]
- In progress
* IR SVE
== Progress ==
* LLVM 7.1.0 Release for ARM & AArch64 [LLVM-546]
- Fixed our infra scripts to work for 7.1.0 (looks like it's the
first ever minor release since the new numbering scheme was
introduced)
- AArch64 is ready and green, ARM still in progress
* [Thumb GlobalISel] Bugfixes
== Progress ==
* [Thumb GlobalISel] Support global variables [LLVM-540]
- Committed upstream
* [Thumb GlobalISel] Support G_CTLZ [LLVM-543]
- Committed upstream
- We now have the same level of support for Thumb2 and ARM mode
* LLVM 8.0.0 Release for ARM & AArch64 [LLVM-526]
- Tested and
== Progress ==
* [Thumb GlobalISel] Support control flow [LLVM-530]
- Committed upstream
* [Thumb GlobalISel] Support accessing the stack [LLVM-527]
- Committed upstream
* [Thumb GlobalISel] Support floating point [LLVM-531]
- Committed upstream
* LLVM 8.0.0 Release for ARM & AArch64
== Progress ==
* LLVM 8.0.0 Release for ARM & AArch64 [LLVM-526]
- LLVM 8.0.0 is out!
* [Thumb GlobalISel] Bugfixes [LLVM-544]
- Patch for alignment issues ready to commit next week
- With the patch, we can build clang successfully, but it fails some
of its tests
- Investigated one of
== Progress ==
* Out of office on Monday
* [Thumb GlobalISel] Support G_GEP [LLVM-532]
- Committed upstream
* [Thumb GlobalISel] Support G_ICMP [LLVM-528]
- Committed upstream
* [Thumb GlobalISel] Support G_SELECT [LLVM-529]
- Almost ready to commit
* LLVM 8.0.0 Release for ARM &
== Progress ==
* [Thumb GlobalISel] Support G_SELECT [LLVM-529]
- Committed upstream
* [Thumb GlobalISel] Support control flow [LLVM-530]
- Committed support for branches
- Support for PHI in progress
* LLVM 8.0.0 Release for ARM & AArch64 [LLVM-526]
- rc2 uploaded, no changes from rc1
== Progress ==
* Out of office on Monday
* [Thumb GlobalISel] Support G_SHL, G_ASHR, G_LSHR [LLVM-517]
- Committed upstream
* [Thumb GlobalISel] Support G_SDIV and G_UDIV [LLVM-516]
- Most of the work done, ready to commit next week
* LLVM 8.0 Release for ARM & AArch64 [LLVM-526]
-
== Progress ==
* Out of office on Friday
* [Thumb GlobalISel] Support divisions [LLVM-516]
- Committed upstream
* [Thumb GlobalISel] Support G_GEP [LLVM-532]
- Ready to commit next week
* LLVM 8.0.0 Release for ARM & AArch64 [LLVM-526]
- Posted binaries for rc1
- Created a bug report
== Progress ==
* LLVM 7.1.0 Release for ARM & AArch64 [LLVM-546]
- Final candidate build in progress
* [GlobalISel] Map and select G_FCONSTANT [LLVM-552]
- Committed upstream
* [GlobalISel] Better support for small types [LLVM-553]
- In progress
== Plan ==
* LLVM-546, LLVM-553
== Progress ==
* Out of office 1 day (Thursday)
* [Thumb GlobalISel] Bugfixes [LLVM-544]
- The test-suite compiles and executes without failures (with
fallback to DAG ISel)
- We get some bus errors in the selfhost, which are due to unaligned
64-bit stores. Apparently when alignment checks
== Progress ==
* [GlobalISel] Add support for integers > 32 bits wide [LLVM-310]
- While looking into this I found and fixed a bug in the generic
part of IRTranslator, which reduced the number of fallbacks on the ARM
test-suite by about 20%
- Currently working on lowering function calls etc
== Progress ==
* Out of office 22 & 24 May
* [GlobalISel] Refactor CallLowering [LLVM-568]
- In progress, likely going to take a while
- Found a minor bug in the lowering for AArch64 (I can get it to
crash on some edge case), not sure if it's worth fixing independently
since it gets fixed
== Progress ==
* Out of office on Friday (bank holiday)
* [GlobalISel] Refactor CallLowering [LLVM-568]
- Patches upstream
* [ARM GlobalISel] Add support for integers > 32 bits wide [LLVM-310]
- Started looking into call lowering for 64-bit types
* LLVM SPEC2k6 Performance Analysis
== Progress ==
* Out of office on Friday (sick)
* [GlobalISel] Better support for small types [LLVM-553]
- Committed upstream
* GlobalISel
- quickfix for a DBG_VALUE-related bug
- code reviews
* SVE code reviews
* Catching up on Connect / EuroLLVM
== Plan ==
* More of the same
* Out
== Progress ==
* Out of office 1 day (public holiday)
* [GlobalISel] Better support for small types [LLVM-553]
- Fixed the bug that I'd been looking into
- Committed support for several instructions, only 3 left to commit next week
* IR SVE Reviews [LLVM-545]
- Looked into the patches for
== Progress ==
* Short week (Out of office 22 - 24 April)
* [GlobalISel] Better support for small types [LLVM-553]
- Investigated my bug some more, it doesn't seem to be related to my
recent patches but rather an existing issue which is exposed because
we select more functions now
- Might be
== Progress ==
* LLVM SPEC2k6 Performance Analysis [LLVM-134]
- Still working around perf version mismatches, going to investigate
if we can use a newer version of perf to collect data
- Had a look at the assembly for sphinx from gcc-6, clang-3.9.1 and
clang-8.0.0, but going to wait for
== Progress ==
* [GlobalISel] Refactor CallLowering [LLVM-568]
- Committed upstream
* [ARM GlobalISel] Add support for integers > 32 bits wide [LLVM-310]
- In progress
* LLVM SPEC2k6 Performance Analysis [LLVM-134]
- Got some results with clang-3.9.1 and clang-8.0.0, trying to work
around
== Progress ==
* Investigate running benchmarks in containers [TCWG-1513]
- Faffing about with our benchmarking scripts, not sure how to test
changes without disrupting our infrastructure
- Cooked up some viz scripts so I can easily look at the noise
levels in benchmark results with/without
== Progress ==
* Short week (Out of office 18 - 19 April)
* LLVM 7.1.0 Release for ARM & AArch64 [LLVM-546]
- Uploaded binaries for both ARM & AArch64
* [GlobalISel] Better support for small types [LLVM-553]
- Still in progress (currently investigating a bug)
* Catching up on Connect
==
== Progress ==
* Investigate running benchmarks in containers [TCWG-1513]
- Cleaned and uploaded scripts for comments
- mcf still hangs, but only when run with clang; investigating root cause
* SVE IR fuzzer [LLVM-586]
- Made some progress with the prototype but it still needs work
*
== Progress ==
* Investigate running benchmarks in containers [TCWG-1513]
- Discussed the noise levels with the team and we decided to
continue with this
- mcf hangs, need to investigate the cause
- WIP: cleaning up the scripts so I can send a sensible patch for review
* IR SVE reviews
== Progress ==
* Investigate running benchmarks in containers [TCWG-1513]
- Addressed review comments, merged changes to dockerfiles
- Fixed mcf on AArch64; also managed to run on armv7 but with some failures
* SVE IR fuzzer [LLVM-586]
- Didn't get to work much on it, but rebuilt it with
== Progress ==
* Investigate running benchmarks in containers [TCWG-1513]
- Finally merged, after a few more iterations and testing!
- Doesn't work for AArch32 yet but I think I have a fix
* Use newer perf for benchmarking [TCWG-1512]
- Tried 4.15.0-62 generic on the TK1, doesn't seem to
== Progress ==
* LLVM 9.0.0 rc1 binaries uploaded
- Ran into one cross-platform issue (x86, AArch64, ARM etc)
- Opened a bug for libfuzzer tests on AArch64
* Use ninja in release job [LLVM-536]
- Done
* Investigate running benchmarks in containers [TCWG-1513]
- Seems to work, except for
== Progress ==
* LLVM 8.0.1 rc4 binaries uploaded
* Buildbot and kernel builds monitoring
- Investigated/reported/fixed a couple of issues
- Tried to reproduce a clang-native-arm-lnt-perf failure that's been
keeping the bot red since the 3rd of July, but it turns out to be very
tricky
*
== Progress ==
* LLVM 8.0.1 final binaries uploaded
* Use ninja in release job [LLVM-536]
- Patches ready, but waiting for 9.0.0-rc1 so I can test (was
supposed to come out this week but got postponed to Monday)
* Investigate running benchmarks in containers [TCWG-1513]
- Still having
== Progress ==
* Out of office on Friday
* Use newer perf for benchmarking [TCWG-1512]
- Switched benchmarking to use bionic containers, with perf 4.18.0;
seems to work
* Investigate running benchmarks in containers [TCWG-1513]
- Done
* Uploaded LLVM 9.0.0-rc5 and rc6
* SVE IR fuzzer
== Progress ==
* Catching up after holidays
* [GlobalISel] Refactor CallLowering [LLVM-568]
- Still in progress, but I fixed the AMDGPU failure
- Decided to go a bit deeper than initially intended, since it gets
really awkward otherwise
* IR SVE Reviews [ LLVM-545]
- New version of the
== Progress ==
* LLVM 9.0.1
- Trying to bisect the arm failures
* Triaging check-lldb failures on AArch64 [LLVM-512]
- Finished with the unexpected failures
- There are still some unexpected passes, but Omair has agreed to
look into them
* Morello
- Managed to build android and
== Progress ==
* Out of office 1 day
* Buildbot monitoring
- Moved the buildbots to pull from github
* Trying to setup a build environment on ex40-01
- Gave up on the tcwg-sq-01/2 boards because they seemed too unstable
* Still no access to Morello docs
* Playing with lldb python
== Progress ==
* clang-tidy workshop (and associated prep)
- I think this went really well, we got good feedback from some of
the participants
* Trying to setup a build environment on tcwg-sq-02.tcwglab
- Mostly so I can deploy the SVE fuzzer there, but maybe for other things too
- All the
== Progress ==
* Out of office on Thursday
* LLVM 9.0.1
- Uploaded ARM & AArch64 binaries for rc1
- ARM: opened 2 bug reports (asan and cfi tests failing)
* Triaging check-lldb failures on AArch64 [LLVM-512]
- Opened a few more bug reports
- Got one nasty failure that I want to look
== Progress ==
* Triaging check-lldb failures on AArch64 [LLVM-512]
- Opened 4 bug reports
- One of them got a lot of attention so I was asked to upload more
logs/try various things
- Still have a couple of test failures to look into
* Morello
- First contact with the team
- Started
== Progress ==
* Out of office on Monday
* Catching up after Connect
* Minor buildbot fix
* IR SVE Reviews [LLVM-545]
- Another round on the size queries patch
* SVE IR fuzzer [LLVM-586]
- Waiting for the size queries patch to get merged so I can give it a spin
* Support Arran fat pointers
== Progress ==
* Support Morello fat pointers in LLDB [LLVM-597]
- Read an intro to Cheri (research project that Morello is based on)
- Read more LLDB docs
* Started writing annual review
* Setup VM for a clang-tidy workshop that I'm co-organizing as part of
the Stockholm LLVM socials
==
== Progress ==
* LLVM 9.0.1
- Had trouble with our TK1 machine
- Trying to build rc3 on one of the buildbots
- AArch64 rc3 looks fine
* Morello
- Got lldb-server working on android and it seems to behave fine
- Working on getting the lldb test-suite to work in remote mode with the
== Progress ==
* More Morello (updating for new capability encoding)
== Plan ==
* More Morello
* Tiny bit GlobalISel
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== Progress ==
* Out of office 2 days
* More Morello (updating for new capability encoding)
== Plan ==
* More Morello
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== Progress ==
* More EuroLLVM submissions reviews
* More investigations into Morello bare metal debugging
* Started looking into updating lldb for the latest Morello architecture
changes
* Asked Adhemerval to look into PR44157
== Plan ==
* More Morello
* Keep an eye out for 10.0.0 - rc1
== Progress ==
* Updating lldb for the latest Morello architecture changes
* Started running the tests for llvm 10.0.0-rc1
== Plan ==
* Check up on the release
* More Morello
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== Progress ==
* More Morello (updating for new capability encoding)
* Tiny amount of GlobalISel arm32 maintenance (not committed yet)
== Plan ==
* More Morello
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== Progress ==
* More Morello (updating for new capability encoding)
* Went to the embassy to get my passport
* Read a couple ARM policy refreshers...
== Plan ==
* More Morello
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Hi Ana,
I don't know anything about the POC myself, but I'm forwarding this so our
QEMU folks can answer.
Cheers,
Diana
-- Forwarded message -
From: Ana Pazos
Date: Fri, 10 Jan 2020 at 19:08
Subject: about QEMU support for SVE2 POC
To: diana.pi...@linaro.org
Cc: Ana Pazos
== Progress ==
* Out of office for 2 days
* Reviewed EuroLLVM submissions
* A bit more investigation into Morello bare metal debugging
== Plan ==
* PR44157
* Morello bare metal debugging
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