On 23/05/14 08:50, Ulf Hansson wrote:
On 23 May 2014 09:13, Srinivas Kandagatla
srinivas.kandaga...@linaro.org wrote:
Hi Ulf,
I like to get this patches for v3.16, any chance of considering these
patches to v3.16 ?
I promise to have them properly reviewed early next week, sorry for
taking
On Thu, May 15, 2014 at 11:36 AM, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds wrappers for readl/writel functions used in the driver. The
reason for this wrappers is to accommodate SOCs like Qualcomm which has
requirement
On Thu, May 15, 2014 at 11:37 AM, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
Most of the Qcomm SD card controller registers must be updated to the MCLK
domain so subsequent writes to registers will be ignored until 3 clock cycles
have
On Thu, May 15, 2014 at 11:37 AM, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds 8bit bus enable to variant structure giving more flexibility
to the driver to support more SOCs which have different clock register layout.
On Thu, May 15, 2014 at 11:37 AM, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds ddrmode mask to variant structure giving more flexibility
to the driver to support more SOCs which have different datactrl register
layout.
On Thu, May 15, 2014 at 11:37 AM, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds edge support for data and command out to variant structure
giving more flexibility to the driver to support more SOCs which have
different clock
Thanks Linus W.
On 23/05/14 10:09, Linus Walleij wrote:
On Thu, May 15, 2014 at 11:37 AM, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
On some SOCs like Qcom there are explicit bits in the command register
to specify if its a data transfer
On Thu, May 15, 2014 at 11:37 AM, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds support to fbclk that is used to latch data and
cmd on some controllers like SD Card controller in Qcom SOC.
Signed-off-by: Srinivas Kandagatla
On Thu, May 15, 2014 at 11:37 AM, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
On Qcom SD card controller, cclk is mclk and mclk should be directly
controlled by the driver.
This patch adds support to control mclk directly in the driver, and
On 23/05/14 10:12, Linus Walleij wrote:
On Thu, May 15, 2014 at 11:37 AM, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds support to fbclk that is used to latch data and
cmd on some controllers like SD Card controller in Qcom
On 23/05/14 10:31, Linus Walleij wrote:
On Thu, May 15, 2014 at 11:38 AM, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
MCIFIFOCNT register behaviour on Qcom chips is very different than the other
pl180 integrations. MCIFIFOCNT register
Hi Linus W,
On 23/05/14 10:31, Linus Walleij wrote:
static int mmci_qcom_pio_read(struct mmci_host *host, char *buffer,
unsigned int remain)
{
u32 *ptr = (u32*) buffer;
unsigned int count = 0;
unsigned int words;
unsigned int fifo_size =
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
Thankyou Linus W and everyone for reviewing RFC to v3 patches.
This patch series adds Qualcomm SD Card Controller support in pl180 mmci
driver. QCom SDCC is basically a pl180, but bit more customized, some of the
register layouts and
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch converts the register bits in the header file to use BIT(()
macro, which looks much neater.
No functional changes done.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
---
drivers/mmc/host/mmci.h | 208
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds a fake Qualcomm ID 0x00051180 to the amba_ids, as Qualcomm
SDCC controller is pl180, but amba id registers read 0x0's.
The plan is to remove SDCC driver totally and use mmci as the main SD
controller driver for Qualcomm
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds ddrmode mask to variant structure giving more flexibility
to the driver to support more SOCs which have different datactrl register
layout.
Without this patch datactrl register is updated with wrong ddrmode mask on non
ST
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
MCIFIFOCNT register behaviour on Qcom chips is very different than the other
pl180 integrations. MCIFIFOCNT register contains the number of
words that are still waiting to be transferred through the FIFO. It keeps
decrementing once the host
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
On some SOCs like Qcom there are explicit bits in the command register
to specify if its a data transfer command or not. So this patch adds
support to such bits in variant data, giving more flexibility to the
driver.
Signed-off-by:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
On Controllers like Qcom SD card controller where cclk is mclk and mclk should
be directly controlled by the driver.
This patch adds support to control mclk directly in the driver, and also
adds explicit_mclk_control and cclk_is_mclk flags
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds specifics of clk and datactrl register on Qualcomm SD
Card controller. This patch also populates the Qcom variant data with
these new values specific to Qualcomm SD Card Controller.
Signed-off-by: Srinivas Kandagatla
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds wrappers for readl/writel functions used in the driver. The
reason for this wrappers is to accommodate SOCs like Qualcomm which has
requirement for delaying the write for few cycles when writing to its SD Card
Controller
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds edge support for data and command out to variant structure
giving more flexibility to the driver to support more SOCs which have
different clock register layout.
Without this patch other new SOCs like Qcom will have to add
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds 8bit bus enable to variant structure giving more flexibility
to the driver to support more SOCs which have different clock register layout.
Without this patch other new SOCs like Qcom will have to add more code
to special
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
Instance of this IP on Qualcomm's SOCs has bit different layout for datactrl
register. Bit position datactrl[16:4] hold the true block size instead of power
of 2.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
On 05/22/2014 07:38 PM, Kumar Gala wrote:
On May 22, 2014, at 11:24 AM, Georgi Djakov gdja...@mm-sol.com wrote:
This patch adds support for the global clock controller found on
the APQ8084 based devices.
The APQ8084 and MSM8974 share a lot of clock data, so instead of
duplicating all the
On 05/22/2014 08:22 PM, Stephen Boyd wrote:
On 05/22/14 09:24, Georgi Djakov wrote:
diff --git a/drivers/clk/qcom/gcc-msm8974.c b/drivers/clk/qcom/gcc-msm8974.c
index 58cb2f5..c2a8d77 100644
--- a/drivers/clk/qcom/gcc-msm8974.c
+++ b/drivers/clk/qcom/gcc-msm8974.c
@@ -204,6 +204,12 @@ static
This patchset adds basic support for the Qualcomm Snapdragon 805 APQ8084 SoC.
The first two patches add device-tree files for the SoC and the board, the
third adds a board compatible string to the DT machine descriptor.
The last one adds information about the low-level debug UART base address
to
Add information about the APQ8084 debug UART physical and virtual
addresses in the DEBUG_QCOM_UARTDM Kconfig help section.
Requires: https://lkml.org/lkml/2014/4/14/312
Signed-off-by: Georgi Djakov gdja...@mm-sol.com
---
arch/arm/Kconfig.debug |1 +
1 file changed, 1 insertion(+)
diff --git
Add device-tree file for APQ8084-MTP board, which belongs
to the Snapdragon 805 family.
Signed-off-by: Georgi Djakov gdja...@mm-sol.com
---
arch/arm/boot/dts/Makefile |3 ++-
arch/arm/boot/dts/qcom-apq8084-mtp.dts |6 ++
2 files changed, 8 insertions(+), 1 deletion(-)
Add support for the Qualcomm Snapdragon 805 APQ8084 SoC. It is
used on APQ8084-MTP and other boards.
Signed-off-by: Georgi Djakov gdja...@mm-sol.com
---
arch/arm/boot/dts/qcom-apq8084.dtsi | 179 +++
1 file changed, 179 insertions(+)
create mode 100644
2014-05-23 17:12 GMT+02:00 Georgi Djakov gdja...@mm-sol.com:
Add information about the APQ8084 debug UART physical and virtual
addresses in the DEBUG_QCOM_UARTDM Kconfig help section.
Requires: https://lkml.org/lkml/2014/4/14/312
Signed-off-by: Georgi Djakov gdja...@mm-sol.com
---
The following changes since commit c9eaa447e77efe77b7fa4c953bd62de8297fd6c5:
Linux 3.15-rc1 (2014-04-13 14:18:35 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom.git
tags/qcom-defconfig-for-3.16
for you to fetch changes up to
On 04/24/14 09:31, Andy Gross wrote:
+
+static const struct of_device_id gsbi_dt_match[] = {
+ { .compatible = qcom,gsbi-v1.0.0, },
+};
Eek. This isn't NULL terminated.
-8---
From: Stephen Boyd sb...@codeaurora.org
Subject: [PATCH] soc: qcom: Terminate gsbi of match table
Failure
From: Stephen Boyd sb...@codeaurora.org
Date: Thu, 22 May 2014 14:00:08 -0700
This set of patches properly documents the micrel ks8851 spi ethernet
controller, converts to devm_regulator_get_optional() to make error
paths slightly simpler, and finally adds supports for another
optional
This simplifies error paths and removes the need to
regulator_put().
Cc: Nishanth Menon n...@ti.com
Signed-off-by: Stephen Boyd sb...@codeaurora.org
---
drivers/net/ethernet/micrel/ks8851.c | 11 +++
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git
This set of patches properly documents the micrel ks8851 spi ethernet
controller, converts to devm_regulator_get_optional() to make error
paths slightly simpler, and finally adds supports for another
optional regulator and a reset gpio. This allows me to use the ks8851
on my MSM8960 CDP board.
Allow the ks8851 driver to enable an optional 1.8V vdd_io
regulator and assert the reset pin to the phy if a reset gpio is
present in device tree.
Cc: Nishanth Menon n...@ti.com
Signed-off-by: Stephen Boyd sb...@codeaurora.org
---
drivers/net/ethernet/micrel/ks8851.c | 54
Users are currently just providing ks8851 as the compatible for
this driver in device tree. Add a compatible string that provides
the vendor name along with the device name to be more explicit.
Signed-off-by: Stephen Boyd sb...@codeaurora.org
---
drivers/net/ethernet/micrel/ks8851.c | 6 ++
On Friday 23 May 2014, Kumar Gala wrote:
Qualcomm ARM Based Device Tree Updates for v3.16
* Added device tree nodes for pinctrl and SDHC for msm8974 SoC/DB8074 board
* Added binding spec for GSBI configuration node
Pulled
On Friday 23 May 2014, Kumar Gala wrote:
Qualcomm ARM Based defconfig Updates for v3.16
* Add a new qcom_defconfig for mach-qcom
* Update msm_defconfig for handling building the old mach-msm
Merged into next/defconfig, thanks!
Arnd
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On Friday 23 May 2014, Kumar Gala wrote:
The following changes since commit c9eaa447e77efe77b7fa4c953bd62de8297fd6c5:
Linux 3.15-rc1 (2014-04-13 14:18:35 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom.git
Quoting Georgi Djakov (2014-05-20 09:50:54)
The address of the blsp2_ahb_clk register is incorrect. Fix it.
Signed-off-by: Georgi Djakov gdja...@mm-sol.com
Applied to clk-next.
Regards,
Mike
---
drivers/clk/qcom/gcc-msm8974.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
On 05/23/14 05:53, srinivas.kandaga...@linaro.org wrote:
@@ -1022,6 +1025,40 @@ mmci_cmd_irq(struct mmci_host *host, struct
mmc_command *cmd,
}
}
+static int mmci_qcom_pio_read(struct mmci_host *host, char *buffer,
+ unsigned int remain)
+{
+ u32 *ptr =
On 05/23/14 16:28, Olof's autobuilder wrote:
Warnings:
1 arch/arm/mach-msm/board-trout-gpio.c:120:2: warning: passing argument
2 of '__raw_writeb' makes pointer from integer without a cast [enabled by
default]
1 arch/arm/mach-msm/board-trout-gpio.c:135:2: warning: passing
Signed-off-by: Bjorn Andersson bjorn.anders...@sonymobile.com
---
drivers/pinctrl/pinctrl-apq8064.c | 21 ++---
1 file changed, 18 insertions(+), 3 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-apq8064.c
b/drivers/pinctrl/pinctrl-apq8064.c
index 23c4c21..3adf9fd 100644
---
Some gpios used for cs-gpios may not be configured for output by
default. In these cases gpio_set_value() won't have any effect
and so the chip select line won't toggle. Request the cs-gpios
and set them to output direction once we know if the chip select
is default high or default low.
Cc: Linus
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