On Wed, May 28, 2014 at 3:57 PM, Srinivas Kandagatla
srinivas.kandaga...@linaro.org wrote:
This doesn't look endianness agnostic. Shouldn't we use ioread32_rep()
to read this fifo?
Is'nt readl endianess aware?
At least once a year read through arch/arm/include/asm/io.h
static inline u32
On Wed, May 28, 2014 at 9:43 PM, Kumar Gala ga...@codeaurora.org wrote:
On May 28, 2014, at 2:05 PM, Linus Walleij linus.wall...@linaro.org wrote:
On Wed, May 28, 2014 at 6:18 PM, Kumar Gala ga...@codeaurora.org wrote:
Just wondering were we stood on:
On Fri, May 9, 2014 at 8:08 PM, Kumar Gala ga...@codeaurora.org wrote:
Drop underscore in spdif_groups to match all other groups.
Signed-off-by: Kumar Gala ga...@codeaurora.org
Patch applied with Andy's ACK, sorry for missing this :-(
Yours,
Linus Walleij
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To unsubscribe from this list:
On Tue, May 13, 2014 at 12:16 AM, Andy Gross agr...@codeaurora.org wrote:
This patch adds pin definitiones for the MSM8x74 TLMM. New definitions
include:
BLSP devices (I2C, UART, SPI, and UIM), mi2s, gp clk, pdm, gcc clk, cci_timer,
cci_i2c, cam_clk, hsic, tsif, sdc3, sdc4, and other
On May 29, 2014, at 3:34 AM, Linus Walleij linus.wall...@linaro.org wrote:
On Wed, May 28, 2014 at 9:43 PM, Kumar Gala ga...@codeaurora.org wrote:
On May 28, 2014, at 2:05 PM, Linus Walleij linus.wall...@linaro.org wrote:
On Wed, May 28, 2014 at 6:18 PM, Kumar Gala ga...@codeaurora.org wrote:
On Apr 24, 2014, at 11:31 AM, Andy Gross agr...@codeaurora.org wrote:
This patch removes direct access of the GSBI registers. GSBI configuration
should be done through the GSBI driver directly.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/tty/serial/msm_serial.c | 48
2014-05-27 14:05 GMT+02:00 Georgi Djakov gdja...@mm-sol.com:
On 05/26/2014 08:17 PM, Matthias Brugger wrote:
2014-05-26 15:45 GMT+02:00 Georgi Djakov gdja...@mm-sol.com:
On 23.05.14, 19:39, Matthias Brugger wrote:
2014-05-23 17:12 GMT+02:00 Georgi Djakov gdja...@mm-sol.com:
Add information
* Move SoC peripherals into an SoC container node
* Move serial enabling into board file (qcom-msm8960-cdp.dts)
* Cleanup cpu node to match binding spec, enable-method and compatible
should be per cpu, not part of the container
* Drop interrupts property from l2-cache node as its not part of the
Add basic APQ8064 SoC include device tree and support for basic booting on
the IFC6410 board. Also, keep dtb build list and qcom_dt_match in sorted
order.
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
v2:
* Fix gsbi controller reg address
arch/arm/boot/dts/Makefile | 8
On Thu, May 29, 2014 at 10:14:35AM -0500, Kumar Gala wrote:
On Apr 24, 2014, at 11:31 AM, Andy Gross agr...@codeaurora.org wrote:
This patch removes direct access of the GSBI registers. GSBI configuration
should be done through the GSBI driver directly.
Signed-off-by: Andy Gross
* Move SoC peripherals into an SoC container node
* Move serial enabling into board file (qcom-msm8660-surf.dts)
* Cleanup cpu node to match binding spec, enable-method and compatible
should be per cpu, not part of the container
* Add GSBI node and configuration of GSBI controller
If we have a PCI config space specified in something like a ranges
property we should treat it as memory type resource.
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
drivers/of/address.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/of/address.c b/drivers/of/address.c
index
On May 29, 2014, at 10:14 AM, Kumar Gala ga...@codeaurora.org wrote:
On Apr 24, 2014, at 11:31 AM, Andy Gross agr...@codeaurora.org wrote:
This patch removes direct access of the GSBI registers. GSBI configuration
should be done through the GSBI driver directly.
Signed-off-by: Andy
Hi Bjorn,
On 27/05/14 18:28, Bjorn Andersson wrote:
Add binding for the Qualcomm Resource Power Manager (RPM) found in 8660, 8960
and 8064 based devices. The binding currently describes the rpm itself and the
regulator subnodes.
Signed-off-by: Bjorn Andersson bjorn.anders...@sonymobile.com
---
Hi Bjorn,
On 27/05/14 18:28, Bjorn Andersson wrote:
Driver for the Resource Power Manager (RPM) found in Qualcomm 8660, 8960 and
8064 based devices. The driver exposes resources that child drivers can operate
on; to implementing regulator, clock and bus frequency drivers.
Signed-off-by: Bjorn
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
arch/arm/configs/qcom_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/qcom_defconfig b/arch/arm/configs/qcom_defconfig
index bfed753..42ebd72 100644
--- a/arch/arm/configs/qcom_defconfig
+++
On May 29, 2014, at 11:19 AM, Srinivas Kandagatla
srinivas.kandaga...@linaro.org wrote:
+= SUBDEVICES
+
+The RPM exposes resources to its subnodes. The below bindings specify the
set
+of valid subnodes that can operate on these resources.
Why should these devices be on sub nodes?
Add binding for the Qualcomm Resource Power Manager (RPM) found in 8660, 8960
and 8064 based devices. The binding currently describes the rpm itself and the
regulator subnodes.
Signed-off-by: Bjorn Andersson bjorn.anders...@sonymobile.com
---
On 29/05/14 17:30, Kumar Gala wrote:
On May 29, 2014, at 11:19 AM, Srinivas Kandagatla
srinivas.kandaga...@linaro.org wrote:
+= SUBDEVICES
+
+The RPM exposes resources to its subnodes. The below bindings specify the set
+of valid subnodes that can operate on these resources.
Why should
On Wed, May 28, 2014 at 10:06 AM, Kumar Gala ga...@codeaurora.org wrote:
It is the purpose so that as we see common patterns between either
drivers/soc/VENDOR we can refactor in the future. However, we need to all
a little time for those patterns to emerge rather than shoe horning in
On Wed, May 28, 2014 at 9:34 AM, Kumar Gala ga...@codeaurora.org wrote:
On May 27, 2014, at 12:28 PM, Bjorn Andersson
bjorn.anders...@sonymobile.com wrote:
Add binding for the Qualcomm Resource Power Manager (RPM) found in 8660, 8960
and 8064 based devices. The binding currently describes
On Thu 2014-05-15 20:10:13, Paul Bolle wrote:
Daniel,
On Thu, 2014-05-15 at 17:44 +, dwal...@fifo99.com wrote:
On Wed, May 14, 2014 at 11:07:36PM +0200, Paul Bolle wrote:
Commit 1b802ff79f03 (arm: msm: add board file for Nexus One (ie.
mahimahi)) added just board-mahimahi.c. It did
On Thu, May 29, 2014 at 9:19 AM, Srinivas Kandagatla
srinivas.kandaga...@linaro.org wrote:
+- reg:
+ Usage: required
+ Value type: prop-encoded-array
+ Definition: two entries specifying the RPM's message ram and ipc
register
+
+- reg-names:
+ Usage: required
+
On Thu, May 29, 2014 at 9:54 AM, Lee Jones lee.jo...@linaro.org wrote:
diff --git a/include/dt-bindings/mfd/qcom_rpm.h
b/include/dt-bindings/mfd/qcom_rpm.h
new file mode 100644
index 000..277e789
--- /dev/null
+++ b/include/dt-bindings/mfd/qcom_rpm.h
@@ -0,0 +1,142 @@
+/*
+ * This
On Thu, May 29, 2014 at 9:19 AM, Srinivas Kandagatla
srinivas.kandaga...@linaro.org wrote:
+++ b/drivers/mfd/qcom_rpm.c
[...]
+struct qcom_rpm {
+ struct device *dev;
+ struct completion ack;
+ struct mutex lock;
+
+ void __iomem *status_regs;
+ void __iomem
On Thu, May 29, 2014 at 11:03 AM, Kumar Gala ga...@codeaurora.org wrote:
If we have a PCI config space specified in something like a ranges
property we should treat it as memory type resource.
Config space should not be in ranges[1]. We have some cases that are,
but we don't want new ones.
On May 29, 2014, at 3:44 PM, Rob Herring robherri...@gmail.com wrote:
On Thu, May 29, 2014 at 11:03 AM, Kumar Gala ga...@codeaurora.org wrote:
If we have a PCI config space specified in something like a ranges
property we should treat it as memory type resource.
Config space should not be
On Wed, May 28, 2014 at 9:55 AM, Mark Brown broo...@kernel.org wrote:
On Tue, May 27, 2014 at 10:28:41AM -0700, Bjorn Andersson wrote:
+static int rpm_reg_set_voltage(struct regulator_dev *rdev,
+int min_uV, int max_uV,
+unsigned
On Thu, May 29, 2014 at 02:03:40PM -0700, Bjorn Andersson wrote:
Please fix your mailer to word wrap at less than 80 columns so quoted
text is legible.
The hardware in this case is a pmic shared by all cpus in the system, so
when
we set the voltage, state or load of a regulator we merely
On 29/05/14 19:38, Bjorn Andersson wrote:
On Thu, May 29, 2014 at 9:19 AM, Srinivas Kandagatla
srinivas.kandaga...@linaro.org wrote:
+- reg:
+ Usage: required
+ Value type: prop-encoded-array
+ Definition: two entries specifying the RPM's message ram and ipc
register
+
+-
On 29/05/14 20:45, Bjorn Andersson wrote:
On Thu, May 29, 2014 at 9:19 AM, Srinivas Kandagatla
srinivas.kandaga...@linaro.org wrote:
+++ b/drivers/mfd/qcom_rpm.c
the line spacing looks bit odd.
I'll fix
+};
+
+#define RPM_STATUS_REG(rpm, i) ((rpm)-status_regs + (i) * 4)
+#define
Adding Jason Gunthorpe...
On Thu, May 29, 2014 at 3:51 PM, Kumar Gala ga...@codeaurora.org wrote:
On May 29, 2014, at 3:44 PM, Rob Herring robherri...@gmail.com wrote:
On Thu, May 29, 2014 at 11:03 AM, Kumar Gala ga...@codeaurora.org wrote:
If we have a PCI config space specified in
On Thu, May 29, 2014 at 2:18 PM, Mark Brown broo...@kernel.org wrote:
On Thu, May 29, 2014 at 02:03:40PM -0700, Bjorn Andersson wrote:
Please fix your mailer to word wrap at less than 80 columns so quoted
text is legible.
The hardware in this case is a pmic shared by all cpus in the system,
On Thu, May 29, 2014 at 02:59:38PM -0700, Bjorn Andersson wrote:
On Thu, May 29, 2014 at 2:18 PM, Mark Brown broo...@kernel.org wrote:
No, this is awful and there's no way in hell that stuff like this should
be implemented in a driver since there's clearly nothing at all hardware
specific
On Thu, May 29, 2014 at 2:41 PM, Srinivas Kandagatla
srinivas.kandaga...@linaro.org wrote:
Although we will not have more than one rpm in a system and therefore not
instatiate this driver multiple times I do not want to run it off the
global
state.
I agree.
Why not make a separate data
On 5/29/2014 11:24 AM, Bjorn Andersson wrote:
On Wed, May 28, 2014 at 9:34 AM, Kumar Gala ga...@codeaurora.org wrote:
On May 27, 2014, at 12:28 PM, Bjorn Andersson
bjorn.anders...@sonymobile.com wrote:
Add binding for the Qualcomm Resource Power Manager (RPM) found in 8660,
8960
and 8064
On Thu, May 29, 2014 at 03:51:28PM -0500, Kumar Gala wrote:
On May 29, 2014, at 3:44 PM, Rob Herring robherri...@gmail.com wrote:
On Thu, May 29, 2014 at 11:03 AM, Kumar Gala ga...@codeaurora.org wrote:
If we have a PCI config space specified in something like a ranges
property we
On 05/29/14 00:43, Linus Walleij wrote:
On Wed, May 28, 2014 at 3:57 PM, Srinivas Kandagatla
srinivas.kandaga...@linaro.org wrote:
This doesn't look endianness agnostic. Shouldn't we use ioread32_rep()
to read this fifo?
Is'nt readl endianess aware?
At least once a year read through
On Thu, May 29, 2014 at 6:56 PM, Liviu Dudau li...@dudau.co.uk wrote:
On Thu, May 29, 2014 at 03:51:28PM -0500, Kumar Gala wrote:
On May 29, 2014, at 3:44 PM, Rob Herring robherri...@gmail.com wrote:
On Thu, May 29, 2014 at 11:03 AM, Kumar Gala ga...@codeaurora.org wrote:
If we have a PCI
On Thu, May 29, 2014 at 07:29:31PM -0600, Bjorn Helgaas wrote:
On Thu, May 29, 2014 at 6:56 PM, Liviu Dudau li...@dudau.co.uk wrote:
On Thu, May 29, 2014 at 03:51:28PM -0500, Kumar Gala wrote:
On May 29, 2014, at 3:44 PM, Rob Herring robherri...@gmail.com wrote:
On Thu, May 29, 2014 at
...@kernel.org
Signed-off-by: Stephen Boyd sb...@codeaurora.org
---
Reviewed-and-Tested-by: Nishanth Menon n...@ti.com
SDP2430: with next-20140529:
before patch:
https://github.com/nmenon/kernel-test-logs/blob/next-20140529/omap2plus_defconfig/sdp2430.txt
After patch: http://slexy.org/raw/s21sryFhAx
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