+ * some devices may respond with wrong type for
+ * well-known logical units. Force well-known type
+ * to enumerate them correctly.
+ */
+ if (scsi_is_wlun(sdev-lun))
+ sdev-type = TYPE_WLUN;
}
...
My only
Hi Mark,
On Wed, 2014-09-24 at 18:05 +0100, Mark Rutland wrote:
On Wed, Sep 24, 2014 at 05:00:42PM +0100, Ivan T. Ivanov wrote:
On Wed, 2014-09-24 at 15:55 +0100, Mark Rutland wrote:
On Wed, Sep 24, 2014 at 02:58:23PM +0100, Ivan T. Ivanov wrote:
The current ADC is peripheral of
Thanks Mita,
You are right these are careless mistakes.
I will fix all of them and upload a new version shortly.
__ufshcd_send_uic_cmd() is called with host_lock held here, but
host_lock is acquired again in __ufshcd_send_uic_cmd(). So it causes
recursive deadlock.
Correct I forgot to
On Wed, 2014-09-24 at 16:48 +0530, Kiran Padwal wrote:
There is no need to init .owner field.
Based on the patch from Peter Griffin peter.grif...@linaro.org
mmc: remove .owner field for drivers using module_platform_driver
This patch removes the superflous .owner field for drivers which
This change replaces use of arm_pm_restart with recently introduced
reset mechanism in Linux kernel called restart_notifier.
Choosing priority 128, which is default priority, as according to
documentation, this mechanism is sufficient to restart the entire system.
Cc: Guenter Roeck
From: Subhash Jadavani subha...@codeaurora.org
Some devices may respond with wrong type for well-known logical units.
This patch forces well-known type for devices which doesn't report it
correct.
Signed-off-by: Subhash Jadavani subha...@codeaurora.org
Signed-off-by: Sujit Reddy Thumma
This patch seies introduces support for power management in the driver as well
as vendor specific initialization - registers, clocks, voltage regulators etc.
It includes also a rework for the init sequence and other PM pre-requisite such
as write protection support, handling well-known LUN,
From: Sujit Reddy Thumma sthu...@codeaurora.org
UFS devices are powered by at most three external power supplies -
- VCC - The flash memory core power supply, 2.7V to 3.6V or 1.70V to 1.95V
- VCCQ - The controller and I/O power supply, 1.1V to 1.3V
- VCCQ2 - Secondary controller and/or I/O power
From: Raviv Shvili rshv...@codeaurora.org
Add the support for voting of the regulator powering the
host controller logic.
Signed-off-by: Raviv Shvili rshv...@codeaurora.org
Signed-off-by: Subhash Jadavani subha...@codeaurora.org
Signed-off-by: Dolev Raviv dra...@codeaurora.org
diff --git
From: Subhash Jadavani subha...@codeaurora.org
Currently reading query descriptor is more tightened to each
descriptor type. This patch generalize the approach and allows
reading any parameter from any query descriptor.
Signed-off-by: Subhash Jadavani subha...@codeaurora.org
Signed-off-by: Dolev
From: Sujit Reddy Thumma sthu...@codeaurora.org
In -hce_enable_notify() callback the vendor specific initialization
may carry out additional DME configuration using UIC commands and
hence the UIC command completion interrupt enable bit should be set
before the post reset notification.
Add retries
From: Sujit Reddy Thumma sthu...@codeaurora.org
Some vendor specific controller versions might need to configure
vendor specific - registers, clocks, voltage regulators etc. to
initialize the host controller UTP layer and Uni-Pro stack.
Provide some common initialization operations that can be
From: Sujit Reddy Thumma sthu...@codeaurora.org
Add generic clock initialization support for UFSHCD platform
driver. The clock info is read from device tree using standard
clock bindings. A generic max-clock-frequency-hz property is
defined to save information on maximum operating clock frequency
From: Subhash Jadavani subha...@codeaurora.org
UFS device may have standard LUs and LUN id could be from 0x00 to 0x7F.
UFS device specification use Peripheral Device Addressing Format
(SCSI SAM-5) for standard LUs.
UFS device may also have the Well Known LUs (also referred as W-LU) which
again
From: Subhash Jadavani subha...@codeaurora.org
Add capability to control the auto bkops during suspend.
If host explicitly enables the auto bkops (background operation) on device
then only device would perform the bkops on its own. If auto bkops is not
enabled explicitly and if the device reaches
- Adding some of the definitions missing in unipro.h, including power
enumeration.
- Read Modify Write Line helper function
- Indication for the type of suspend
Signed-off-by: Dolev Raviv dra...@codeaurora.org
Signed-off-by: Subhash Jadavani subha...@codeaurora.org
Signed-off-by: Yaniv Gardi
From: Sahitya Tummala stumm...@codeaurora.org
The UFS controller clocks can be gated after certain period of
inactivity, which is typically less than runtime suspend timeout.
In addition to clocks the link will also be put into Hibern8 mode
to save more power.
The clock gating can be turned on
From: Sahitya Tummala stumm...@codeaurora.org
The clocks for UFS device will be managed by generic DVFS (Dynamic
Voltage and Frequency Scaling) framework within kernel. This devfreq
framework works with different governors to scale the clocks. By default,
UFS devices uses simple_ondemand governor
From: Yaniv Gardi yga...@codeaurora.org
The maximum power consumption in active is determined by bActiveICCLevel.
The configuration is done by reading max current supported by the
regulators connected to VCC, VCCQ and VCCQ2 rails on the boards, and
reading the current consumption levels from the
From: Subhash Jadavani subha...@codeaurora.org
This patch adds support for UFS device and UniPro link power management
during runtime/system PM.
Main idea is to define multiple UFS low power levels based on UFS device
and UFS link power states. This would allow any specific platform or pci
Sometimes, the device shall report its maximum power and speed
capabilities, but we might not wish to configure it to use those
maximum capabilities.
This change adds support for the vendor specific host driver to
implement power change notify callback.
To enable configuring different power modes
From: Sahitya Tummala stumm...@codeaurora.org
Add freq-table-hz propery for UFS device to keep track of
min max frequencies supported by UFS clocks.
Signed-off-by: Sahitya Tummala stumm...@codeaurora.org
Signed-off-by: Dolev Raviv dra...@codeaurora.org
diff --git
Hi Stan, few comment bellow.
On Wed, 2014-09-24 at 15:56 +0300, Stanimir Varbanov wrote:
The voltage ADC is peripheral of Qualcomm SPMI PMIC chips. It has
15bits resolution and register space inside PMIC accessible across
SPMI bus.
The vadc driver registers itself through IIO interface.
This change adds support for reset driver for apq8074 based platform.
With this we should be able to reboot the board from command prompt.
Cc: Russell King li...@arm.linux.org.uk
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-arm-msm@vger.kernel.org
Signed-off-by: Pramod Gurav
Add support for the temperature alarm peripheral found inside
Qualcomm plug-and-play (QPNP) PMIC chips. The temperature alarm
peripheral outputs a pulse on an interrupt line whenever the
thermal over temperature stage value changes. Implement an ISR
to manage this interrupt.
Register a thermal
On Fri, Sep 19, 2014 at 11:00:02AM +0100, Catalin Marinas wrote:
On Fri, Sep 19, 2014 at 08:09:47AM +0100, Wang, Yalin wrote:
this patch extend the start and end address of initrd to be page aligned,
so that we can free all memory including the un-page aligned head or tail
page of initrd,
Hi Ivan,
On 09/25/2014 03:47 PM, Ivan T. Ivanov wrote:
Hi Stan, few comment bellow.
On Wed, 2014-09-24 at 15:56 +0300, Stanimir Varbanov wrote:
The voltage ADC is peripheral of Qualcomm SPMI PMIC chips. It has
15bits resolution and register space inside PMIC accessible across
SPMI bus.
Please stop putting listname-owner (in this case linux-scsi-owner)
in the CC: list, that goes to me not the list.
--
To unsubscribe from this list: send the line unsubscribe linux-arm-msm in
the body of a message to majord...@vger.kernel.org
More majordomo info at
On Thu, Sep 25, 2014 at 03:31:42PM +0100, Russell King - ARM Linux wrote:
On Fri, Sep 19, 2014 at 11:00:02AM +0100, Catalin Marinas wrote:
On Fri, Sep 19, 2014 at 08:09:47AM +0100, Wang, Yalin wrote:
this patch extend the start and end address of initrd to be page aligned,
so that we can
On Mon, Aug 11, 2014 at 03:45:50PM -0700, Olav Haugan wrote:
+static inline int iommu_map_sg(struct iommu_domain *domain, unsigned long
iova,
+struct scatterlist *sg, unsigned int nents,
+int prot, unsigned long flags)
+{
+ return
The WDT's BITE_TIME warm-reset behavior can be leveraged as a last
resort mechanism for triggering chip reset. Usually, other restart
methods (such as PS_HOLD) are preferrable for issuing a more complete
reset of the chip. As such, keep the priority of the watchdog notifier
low.
Signed-off-by:
This patchset provides support for the Watchdog Timer (WDT) found in the Krait
Processor Sub-system (KPSS) of the MSM8960, APQ8064, and IPQ8064 chips.
This driver is implemented ontop of WATCHDOG_CORE, and therefore its primary
interface is through userspace. The implemantion is currently very
Add a driver for the watchdog timer block found in the Krait Processor
Subsystem (KPSS) on the MSM8960, APQ8064, and IPQ8064.
Signed-off-by: Josh Cartwright jo...@codeaurora.org
---
drivers/watchdog/Kconfig| 13 +++
drivers/watchdog/Makefile | 1 +
drivers/watchdog/qcom-wdt.c | 189
The Qualcomm Krait Processor Sub-system (KPSS) contains one or more
instances of the WDT. Provide documentation on how to describe these in
the device tree.
Signed-off-by: Josh Cartwright jo...@codeaurora.org
---
.../devicetree/bindings/watchdog/qcom-wdt.txt | 22 ++
1
On Thu, Sep 25, 2014 at 12:48:51PM -0500, Josh Cartwright wrote:
Add a driver for the watchdog timer block found in the Krait Processor
Subsystem (KPSS) on the MSM8960, APQ8064, and IPQ8064.
Signed-off-by: Josh Cartwright jo...@codeaurora.org
Hi Josh,
just a couple of minor comments this
On Thu, Sep 25, 2014 at 12:48:53PM -0500, Josh Cartwright wrote:
The WDT's BITE_TIME warm-reset behavior can be leveraged as a last
resort mechanism for triggering chip reset. Usually, other restart
methods (such as PS_HOLD) are preferrable for issuing a more complete
reset of the chip. As
On Thu, Sep 25, 2014 at 12:48:52PM -0500, Josh Cartwright wrote:
The Qualcomm Krait Processor Sub-system (KPSS) contains one or more
instances of the WDT. Provide documentation on how to describe these in
the device tree.
Signed-off-by: Josh Cartwright jo...@codeaurora.org
---
On Thu, Sep 25, 2014 at 11:38:57AM -0700, Guenter Roeck wrote:
On Thu, Sep 25, 2014 at 12:48:51PM -0500, Josh Cartwright wrote:
Add a driver for the watchdog timer block found in the Krait Processor
Subsystem (KPSS) on the MSM8960, APQ8064, and IPQ8064.
Signed-off-by: Josh Cartwright
On Thu, Sep 25, 2014 at 11:43:14AM -0700, Guenter Roeck wrote:
On Thu, Sep 25, 2014 at 12:48:52PM -0500, Josh Cartwright wrote:
[..]
+- timeout-sec : shall contain the default watchdog timeout in seconds,
+if unset, the default timeout is 30 seconds
Hi Josh,
timeout-sec
On Thu, Sep 25, 2014 at 11:41:49AM -0700, Guenter Roeck wrote:
On Thu, Sep 25, 2014 at 12:48:53PM -0500, Josh Cartwright wrote:
The WDT's BITE_TIME warm-reset behavior can be leveraged as a last
resort mechanism for triggering chip reset. Usually, other restart
methods (such as PS_HOLD)
On Thu, 2014-09-25 at 17:02 +0100, Mark Rutland wrote:
On Thu, Sep 25, 2014 at 10:47:15AM +0100, Ivan T. Ivanov wrote:
Hi Mark,
On Wed, 2014-09-24 at 18:05 +0100, Mark Rutland wrote:
On Wed, Sep 24, 2014 at 05:00:42PM +0100, Ivan T. Ivanov wrote:
On Wed, 2014-09-24 at 15:55 +0100,
On Thu, 2014-09-25 at 18:30 +0300, Stanimir Varbanov wrote:
Hi Ivan,
On 09/25/2014 03:47 PM, Ivan T. Ivanov wrote:
Hi Stan, few comment bellow.
On Wed, 2014-09-24 at 15:56 +0300, Stanimir Varbanov wrote:
The voltage ADC is peripheral of Qualcomm SPMI PMIC chips. It has
15bits
On Sep 22, 2014, at 4:54 PM, Kumar Gala ga...@codeaurora.org wrote:
[ some how scm-boot.c got dropped, fixed now ]
The following changes since commit 7d1311b93e58ed55f3a31cc8f94c4b8fe988a2b9:
Linux 3.17-rc1 (2014-08-16 10:40:26 -0600)
are available in the git repository at:
This patchset provides support for the Watchdog Timer (WDT) found in the Krait
Processor Sub-system (KPSS) of the MSM8960, APQ8064, and IPQ8064 chips.
This driver is implemented ontop of WATCHDOG_CORE, and therefore its primary
interface is through userspace. The implemantion is currently very
The WDT's BITE_TIME warm-reset behavior can be leveraged as a last
resort mechanism for triggering chip reset. Usually, other restart
methods (such as PS_HOLD) are preferrable for issuing a more complete
reset of the chip. As such, keep the priority of the watchdog notifier
low.
Signed-off-by:
Add a driver for the watchdog timer block found in the Krait Processor
Subsystem (KPSS) on the MSM8960, APQ8064, and IPQ8064.
Signed-off-by: Josh Cartwright jo...@codeaurora.org
---
drivers/watchdog/Kconfig| 13
drivers/watchdog/Makefile | 1 +
drivers/watchdog/qcom-wdt.c | 186
The Qualcomm Krait Processor Sub-system (KPSS) contains one or more
instances of the WDT. Provide documentation on how to describe these in
the device tree.
Signed-off-by: Josh Cartwright jo...@codeaurora.org
---
.../devicetree/bindings/watchdog/qcom-wdt.txt | 24 ++
1
Srinivas Kandagatla srinivas.kandaga...@linaro.org writes:
On 24/09/14 16:22, Kevin Hilman wrote:
Srinivas Kandagatla srinivas.kandaga...@linaro.org writes:
since commit 31964ffebbb9 (tty: serial: msm: Remove direct access to
GSBI)'
serial hangs if earlyprintk are enabled.
This hang is
On Fri, Sep 19, 2014 at 11:00:02AM +0100, Catalin Marinas wrote:
On Fri, Sep 19, 2014 at 08:09:47AM +0100, Wang, Yalin wrote:
this patch extend the start and end address of initrd to be page
aligned, so that we can free all memory including the un-page
aligned head or tail page of
On 09/25/2014 03:51 PM, Josh Cartwright wrote:
The Qualcomm Krait Processor Sub-system (KPSS) contains one or more
instances of the WDT. Provide documentation on how to describe these in
the device tree.
Signed-off-by: Josh Cartwright jo...@codeaurora.org
Reviewed-by: Guenter Roeck
On 09/25/2014 03:51 PM, Josh Cartwright wrote:
The WDT's BITE_TIME warm-reset behavior can be leveraged as a last
resort mechanism for triggering chip reset. Usually, other restart
methods (such as PS_HOLD) are preferrable for issuing a more complete
reset of the chip. As such, keep the
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