On 8 October 2014 05:29, Rafael J. Wysocki wrote:
> So can you please send me links to the patches? I probably can find them,
> but honestly I have too little time for other stuff already.
Sure:
https://patchwork.kernel.org/patch/4876641/
https://patchwork.kernel.org/patch/4876651/
https://patc
On 09/29/2014 05:12 PM, Stephen Boyd wrote:
I'm also auditing clock
drivers to find potential brokenness.
These are places where we re-enter the framework under drivers/clk/. It
looks like sirf can be ported to use determine_rate() and something like
my "safe parent" patch. Tegra is concer
On Tue, Oct 07, 2014 at 04:30:46PM -0700, Bjorn Andersson wrote:
> On Tue 07 Oct 02:54 PDT 2014, Kiran Padwal wrote:
>
> > On Tuesday 07 October 2014 06:42 AM, Bjorn Andersson wrote:
> > > From: Courtney Cavin
> > >
> > > Signed-off-by: Courtney Cavin
> > > Signed-off-by: Bjorn Andersson
> > >
On Tuesday, October 07, 2014 09:00:16 AM Viresh Kumar wrote:
> On 7 October 2014 04:23, Rafael J. Wysocki wrote:
> > I'm still seeing discussion going on about patch [1/4], though.
>
> That's V1's 1/4 and we finalized V2..
>
> > Is that irrelevant?
>
> No.
>
> > Also I'd prefer Viresh to tell
On Tue 07 Oct 02:54 PDT 2014, Kiran Padwal wrote:
> On Tuesday 07 October 2014 06:42 AM, Bjorn Andersson wrote:
> > From: Courtney Cavin
> >
> > Signed-off-by: Courtney Cavin
> > Signed-off-by: Bjorn Andersson
> > ---
> > drivers/input/misc/Kconfig | 12 +++
> > drivers/input/misc/M
On 10/07/2014 02:41 PM, Lina Iyer wrote:
@@ -144,7 +148,27 @@
};
};
- saw_l2: regulator@f9012000 {
+ saw0: power-controller@f9089000 {
+ compatible = "qcom,msm8974-saw2-v2.1-cpu";
+ reg = <0xf90
On 10/07/2014 03:10 PM, Josh Cartwright wrote:
On Thu, Oct 02, 2014 at 12:08:38PM -0700, Stephen Boyd wrote:
[..]
On 10/01/14 11:15, Josh Cartwright wrote:
Something like this perhaps:
timer@200a000 {
compatible = "qcom,kpss-timer", "qcom,msm-timer";
int
On Thu, Oct 02, 2014 at 12:08:38PM -0700, Stephen Boyd wrote:
[..]
> On 10/01/14 11:15, Josh Cartwright wrote:
> > The percpu-ness of the two WDTs makes configuration even more
> > interesting, as it's possible you'd want to independently configure
> > timeouts for CPU0_WDT0 and CPU1_WDT0, supporti
SPM is a hardware block that controls the peripheral logic surrounding
the application cores (cpu/l$). When the core executes WFI instruction,
the SPM takes over the putting the core in low power state as
configured. The wake up for the SPM is an interrupt at the GIC, which
then completes the rest
Add cpuidle driver interface to allow cpus to go into C-States. Use the
cpuidle DT interface, common across ARM architectures, to provide the
C-State information to the cpuidle framework.
Supported modes at this time are Standby and Standalone Power Collapse.
Signed-off-by: Lina Iyer
---
.../bi
Hi,
This v8 revision of the cpuidle driver is available at
git.linaro.org:/people/lina.iyer/linux-next cpuidle-v8
Changes since v7:
[ https://www.mail-archive.com/linux-arm-msm@vger.kernel.org/msg11199.html ]
- Address review comments
- Tested on 8974 but not 8084
- WFI renamed to Standby
- Upda
Add allowable C-States for each cpu using the cpu-idle-states node.
Support standby and standalone power collapse (power down that does not
affect any SoC idle states) for each cpu.
Signed-off-by: Lina Iyer
---
arch/arm/boot/dts/qcom-apq8084.dtsi | 20
1 file changed, 20 ins
Add allowable C-States for each cpu using the cpu-idle-states node.
Support Standby and Standalone power collapse (power down that does not
affect any SoC idle states) for each cpu.
Signed-off-by: Lina Iyer
---
arch/arm/boot/dts/qcom-msm8974.dtsi | 20
1 file changed, 20 ins
Add interface layer to abstract and handle hardware specific
functionality for executing various cpu low power modes in QCOM
chipsets.
QCOM cpus support multiple low power modes. The C-States are defined as -
* Standby
* Retention (clock gating at lower power)
* Standalone Power Colla
Each Krait CPU in the QCOM 8974 SoC has an SAW power controller to
regulate the power to the cpu and aide the core in entering idle states.
Reference the SAW instance and associate the instance with the CPU core.
Signed-off-by: Lina Iyer
---
arch/arm/boot/dts/qcom-msm8974.dtsi | 26 +
Each Krait CPU in the QCOM 8084 SoC has an SAW power controller to
regulate the power to the cpu and aide the core in entering idle states.
Reference the SAW instance and associate the instance with the CPU core.
Signed-off-by: Lina Iyer
---
arch/arm/boot/dts/qcom-apq8084.dtsi | 26 +
Add cpuidle driver interface to allow cpus to go into C-States. Use the
cpuidle DT interface, common across ARM architectures, to provide the
C-State information to the cpuidle framework.
Supported modes at this time are Standby and Standalone Power Collapse.
Signed-off-by: Lina Iyer
---
.../bi
Each Krait CPU in the QCOM 8084 SoC has an SAW power controller to
regulate the power to the cpu and aide the core in entering idle states.
Reference the SAW instance and associate the instance with the CPU core.
Signed-off-by: Lina Iyer
---
arch/arm/boot/dts/qcom-apq8084.dtsi | 26 +
Add allowable C-States for each cpu using the cpu-idle-states node.
Support standby and standalone power collapse (power down that does not
affect any SoC idle states) for each cpu.
Signed-off-by: Lina Iyer
---
arch/arm/boot/dts/qcom-apq8084.dtsi | 20
1 file changed, 20 ins
Add allowable C-States for each cpu using the cpu-idle-states node.
Support Standby and Standalone power collapse (power down that does not
affect any SoC idle states) for each cpu.
Signed-off-by: Lina Iyer
---
arch/arm/boot/dts/qcom-msm8974.dtsi | 20
1 file changed, 20 ins
Each Krait CPU in the QCOM 8974 SoC has an SAW power controller to
regulate the power to the cpu and aide the core in entering idle states.
Reference the SAW instance and associate the instance with the CPU core.
Signed-off-by: Lina Iyer
---
arch/arm/boot/dts/qcom-msm8974.dtsi | 26 +
Add interface layer to abstract and handle hardware specific
functionality for executing various cpu low power modes in QCOM
chipsets.
QCOM cpus support multiple low power modes. The C-States are defined as -
* Standby
* Retention (clock gating at lower power)
* Standalone Power Colla
SPM is a hardware block that controls the peripheral logic surrounding
the application cores (cpu/l$). When the core executes WFI instruction,
the SPM takes over the putting the core in low power state as
configured. The wake up for the SPM is an interrupt at the GIC, which
then completes the rest
On 07/10/14 19:26, Stephen Boyd wrote:
On 10/07/2014 10:27 AM, Srinivas Kandagatla wrote:
Hi Stephen,
Just noticed this regression while testing the patch on Arndale board.
https://bugs.linaro.org/show_bug.cgi?id=740
If you return value it works correctly right?
Am really not sure, as thi
On Oct 6, 2014, at 8:12 PM, Bjorn Andersson
wrote:
> From: Courtney Cavin
>
> Signed-off-by: Courtney Cavin
> Signed-off-by: Bjorn Andersson
> ---
> .../bindings/input/qcom,pm8941-pwrkey.txt | 43
> 1 file changed, 43 insertions(+)
> create mode 100644
> Docu
On Tue 07 Oct 02:01 PDT 2014, Ivan T. Ivanov wrote:
>
> Hi Bjorn,
>
> On Mon, 2014-10-06 at 18:11 -0700, Bjorn Andersson wrote:
> > These patches add dt bindings and a device driver for the power key block in
> > the Qualcomm PM8941 pmic.
> >
> > Courtney Cavin (2):
> > input: Add Qualcomm PM
On 10/07/2014 10:27 AM, Srinivas Kandagatla wrote:
Hi Stephen,
Just noticed this regression while testing the patch on Arndale board.
https://bugs.linaro.org/show_bug.cgi?id=740
If you return value it works correctly right?
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum
Hi Ivan,
On Tue, Oct 07, 2014 at 12:50:46PM +0300, Ivan T. Ivanov wrote:
> @@ -527,10 +538,55 @@ static int pmic8xxx_kp_probe(struct platform_device
> *pdev)
>
> platform_set_drvdata(pdev, kp);
>
> + if (rows < info->min_rows)
> + rows = info->min_rows;
> +
> + if (c
Hi Stephen,
Just noticed this regression while testing the patch on Arndale board.
https://bugs.linaro.org/show_bug.cgi?id=740
--srini
On 03/10/14 19:07, Stephen Boyd wrote:
On 09/05/14 15:47, Stephen Boyd wrote:
+
+int divider_get_val(unsigned long rate, unsigned long parent_rate,
+
On Tue, Sep 30, 2014 at 7:02 PM, Bjorn Andersson
wrote:
> On Wed 24 Sep 06:09 PDT 2014, Ivan T. Ivanov wrote:
>> I am unable to make this work. of_gpio_simple_xlate() didn't know that
>> GPIO range is offset with 1. Requesting last GPIO return error. And
>> debug output looks weird, for example:
Am 02.10.2014 15:42, schrieb Tanya Brokhman:
> How do you test all of your fastmap fixes? Some of them are not easy to
> reproduce (the pq saving for example). Besides heavy stability testing, I was
> testing my changes manually by
> a lot of dbg prints in the code and analyzing the logs manually
On Sat, 2014-10-04 at 12:51 +0100, Jonathan Cameron wrote:
> On 02/10/14 13:08, Ivan T. Ivanov wrote:
> > +iio maintainers
> >
> > On Thu, 2014-10-02 at 12:29 +0300, Ivan T. Ivanov wrote:
> >> Hi Stan,
> >>
> >> On 09/24/2014 03:56 PM, Stanimir Varbanov wrote:
> >>
> >>
> >>
> >>> +static int vad
On Fri, 2014-10-03 at 16:53 -0700, Bjorn Andersson wrote:
> On Wed 01 Oct 09:30 PDT 2014, Ivan T. Ivanov wrote:
>
> This looks good and I gave it a spin on one of our 8974 devices and verified
> that gpio_keys works :)
>
> Acked-by: Bjorn Andersson
Thank you Bjorn.
Regards,
Ivan
>
> Regards
On Sat, 2014-10-04 at 13:03 +0100, Jonathan Cameron wrote:
> On 01/10/14 17:14, Ivan T. Ivanov wrote:
> > The current ADC is peripheral of Qualcomm SPMI PMIC chips. It has
> > 16 bits resolution and register space inside PMIC accessible across
> > SPMI bus.
> >
> > The driver registers itself throu
On Tuesday 07 October 2014 06:42 AM, Bjorn Andersson wrote:
> From: Courtney Cavin
>
> Signed-off-by: Courtney Cavin
> Signed-off-by: Bjorn Andersson
> ---
> drivers/input/misc/Kconfig | 12 +++
> drivers/input/misc/Makefile|1 +
> drivers/input/misc/pm8941-pwrkey.c | 19
Controller seems to be the same. Just access to it is over SPMI bus
and registers and bits are reshuffled. Hopefully this is nicely
abstracted by regmap helpers.
Signed-off-by: Ivan T. Ivanov
---
.../bindings/input/qcom,pm8xxx-keypad.txt | 1 +
drivers/input/keyboard/pmic8xxx-keypad.c
Fix incorrect dimensions for 'debonce' and 'scan-delay' times.
Now they represent what driver really expect. Add possible
time quants for 'debonce', 'scan-delay' and 'row-hold' times.
Update bindings example.
Signed-off-by: Ivan T. Ivanov
---
Documentation/devicetree/bindings/input/qcom,pm8xxx-k
Abstract access to bit and register definitions to simplify adding
support for similar controller, which be found on SPMI based pm8941.
Group hardware capabilities to controller specific structure, and
pass it to driver, based on compatible string.
Pre-compute minimum number of rows and columns t
These defines are not used by driver. Remove them.
Signed-off-by: Ivan T. Ivanov
---
drivers/input/keyboard/pmic8xxx-keypad.c | 12
1 file changed, 12 deletions(-)
diff --git a/drivers/input/keyboard/pmic8xxx-keypad.c
b/drivers/input/keyboard/pmic8xxx-keypad.c
index 80c6b0e..dd1fc
Hi,
Following set of patches reorganize and add support for keypad
controller found in Qualcomm PMIC pm8941 chip, at least.
Controllers found in pm8058 and pm8921, currently supported by driver,
seems to be similar to controller found in pm8941. Difference is
register access, SSBI vs SPMI bus,
Hi Bjorn,
On Mon, 2014-10-06 at 18:11 -0700, Bjorn Andersson wrote:
> These patches add dt bindings and a device driver for the power key block in
> the Qualcomm PM8941 pmic.
>
> Courtney Cavin (2):
> input: Add Qualcomm PM8941 power key driver
> input: pm8941-pwrkey: Add DT binding document
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