Support powering down the calling cpu, by trapping into SCM. This
termination function triggers the ARM cpu to execute WFI instruction,
causing the power controller to safely power the cpu down.
Caches may be flushed before powering down the cpu. If cache controller
is set to turn off when the
A core can be powered down for cpuidle or when it is hotplugged off. In
either case, the warmboot return address would be different. Allow
setting the warmboot address for a specific cpu, optimize and write to
the firmware, if the address is different than the previously set
address.
Export
We dont need to export the SCM specific cold boot flags to the platform
code. Export only a function to set the cold boot address.
Signed-off-by: Lina Iyer lina.i...@linaro.org
---
arch/arm/mach-qcom/platsmp.c | 21 +++--
drivers/firmware/qcom_scm.c | 41
Hi,
This series of patches adds SCM cold boot clean up and support for warm boot
for QCOM quad core (and dual core) cpus.
v4 Changes:
- Added QCOM_SCM_CPU_DOWN_ prefix for L2 on/off enums, relocated them to be
close
to the function declaration.
v3 Changes:
- Addressed review comments from
Seems required for kexec (where --atags support is mutually exclusive
with --dtb).
Signed-off-by: Rob Clark robdcl...@gmail.com
---
arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
In kexec environment, we are more likely to encounter irq's already
enabled from previous environment. At which point we find that writes
to disable/clear pending irq's are slightly less than useless without
first enabling clocks.
TODO: full blown state read-in so kexec'd kernel can inherit the
On Thu, Feb 26, 2015 at 07:37:44PM -0800, Stephen Boyd wrote:
These frequency tables list the wrong rates. Either they don't
have the correct frequency at all, or they're specified in kHz
instead of Hz. Fix it.
Fixes: c99e515a92e9 clk: qcom: Add IPQ806X LPASS clock controller (LCC)
driver
A core can be powered down for cpuidle or when it is hotplugged off. In
either case, the warmboot return address would be different. Allow
setting the warmboot address for a specific cpu, optimize and write to
the firmware, if the address is different than the previously set
address.
Export
Hi,
This series of patches adds SCM cold boot clean up and support for warm boot
for QCOM quad core (and dual core) cpus.
v3 Changed:
- Addressed review comments from Kumar.
+ Cleaned up the cold boot api and the warm boot api to match
+ Uniform qcom_scm_ prefix
- Add support for
We dont need to export the SCM specific cold boot flags to the platform
code. Export only a function to set the cold boot address.
Signed-off-by: Lina Iyer lina.i...@linaro.org
---
arch/arm/mach-qcom/platsmp.c | 21 +++--
drivers/firmware/qcom_scm.c | 41
Support powering down the calling cpu, by trapping into SCM. This
termination function triggers the ARM cpu to execute WFI instruction,
causing the power controller to safely power the cpu down.
Caches may be flushed before powering down the cpu. If cache controller
is set to turn off when the
On Mar 2, 2015, at 2:30 PM, Lina Iyer lina.i...@linaro.org wrote:
Support powering down the calling cpu, by trapping into SCM. This
termination function triggers the ARM cpu to execute WFI instruction,
causing the power controller to safely power the cpu down.
Caches may be flushed before
On Mon, Mar 02 2015 at 13:52 -0700, Kumar Gala wrote:
On Mar 2, 2015, at 2:30 PM, Lina Iyer lina.i...@linaro.org wrote:
Support powering down the calling cpu, by trapping into SCM. This
termination function triggers the ARM cpu to execute WFI instruction,
causing the power controller to
On Wed, Feb 4, 2015 at 3:39 PM, Stanimir Varbanov svarba...@mm-sol.com wrote:
On 02/03/2015 06:47 PM, Andy Gross wrote:
On Fri, Jan 30, 2015 at 12:04:01PM +0200, Stanimir Varbanov wrote:
From: Joonwoo Park joonw...@codeaurora.org
Add initial pinctrl driver to support pin configuration with
Changes from V3:
Changed tag statistics macros to functions and removed redundant
call to ufsdbg_remove_debugfs().
Other minor changes fixing previous comments.
Dolev Raviv (1):
scsi: ufs: add ioctl interface for query request
Gilad Broner (1):
scsi: ufs: add trace events and dump prints for
From: Sujit Reddy Thumma sthu...@codeaurora.org
Use fault-injection framework to simulate error conditions
in the controller and verify error handling mechanisms
implemented in UFS host controller driver.
This is used only during development and hence
guarded by CONFIG_UFS_FAULT_INJECTION debug
Add trace events to driver to allow monitoring and profilig
of activities such as PM suspend/resume, hibernate enter/exit,
clock gating and clock scaling up/down.
In addition, add UFS host controller register dumps to provide
detailed information in case of errors to assist in analysis
of issues.
From: Lee Susman lsus...@codeaurora.org
Adding debugfs capability for ufshcd.
debugfs attributes introduced in this patch:
- View driver/controller runtime data
- Command tag statistics for performance analisis
- Dump device descriptor info
- Track recoverable errors statistics during
From: Dolev Raviv dra...@codeaurora.org
This patch exposes the ioctl interface for UFS driver via SCSI device
ioctl interface. As of now UFS driver would provide the ioctl for query
interface to connected UFS device.
Signed-off-by: Dolev Raviv dra...@codeaurora.org
Signed-off-by: Noa Rubens
On Sat, Feb 28, 2015 at 12:11:32AM +, Stephen Boyd wrote:
These patches add support for the Scorpion PMU found on devices
such as msm8660, qsd8x50, etc. The first patch is some groundwork
to make functions more generic. Even then we end up copying quite
a bit of code from the Krait part
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