Qualcomm Debug Subsystem clock is used by CoreSight components.
Add required definitions for it. qcom_rpm_resource::status_id is
not used by driver, so just mark it as ~0.
Signed-off-by: Ivan T. Ivanov ivan.iva...@linaro.org
---
Changes since first version:
* Use ~0 initializer for status_id,
apq8016-sbc board is using Dual SPDT USB Switch (TC7USB40MU),
witch is controlled by GPIO to de/multiplex D+/D- USB lines to
USB2513B Hub and uB connector. Add support for this.
Signed-off-by: Ivan T. Ivanov ivan.iva...@linaro.org
---
.../devicetree/bindings/usb/msm-hsusb.txt | 4 ++
Add thermal zones, tsens and eeprom nodes
Signed-off-by: Rajendra Nayak rna...@codeaurora.org
---
arch/arm/boot/dts/qcom-apq8064.dtsi | 108
1 file changed, 108 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi
Add support to calibrate sensors on 8916 family and also add common
functions to read temperature from sensors (This can be reused on
other SoCs having similar TSENS device)
The calibration data is read from eeprom using the generic eeprom
framework apis.
Based on the original code by Siddartha
8960 family of SoCs have the TSENS device as part of a domain
thats not always ON. Hence add .suspend and .resume hooks to
save and restore some of the inited register context.
8960 family has TSENS as part of GCC, hence reuse the GCC
regmap. Also 8960 family had some of the TSENS init sequence
TSENS is Qualcomms' thermal temperature sensor device. It
supports reading temperatures from multiple thermal sensors
present on various QCOM SoCs.
Calibration data is generally read from a eeprom device.
Add a skeleton driver with all the necessary abstractions so
a variety of qcom device
Changes since RFC:
* Added support for 8916 and 8084
* Based off the latest nvmem framework patches [1]
* Minor review fixes for comments mostly from Lina
** I have also added irq support using the hardware
trip point support series [2]. Will post that
out seperately.
This is an attempt to have
Add .calibrate support for 8974 family as part of tsens_ops.
Based on the original code by Siddartha Mohanadoss and Stephen Boyd.
Signed-off-by: Rajendra Nayak rna...@codeaurora.org
---
drivers/thermal/qcom/Makefile | 2 +-
drivers/thermal/qcom/tsens-8974.c | 239
Add thermal zones, tsens and eeprom nodes
Signed-off-by: Rajendra Nayak rna...@codeaurora.org
---
arch/arm/boot/dts/qcom-apq8084.dtsi | 105
1 file changed, 105 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi
Add thermal zones, tsens and eeprom nodes
Signed-off-by: Rajendra Nayak rna...@codeaurora.org
---
arch/arm/boot/dts/qcom-msm8974.dtsi | 105
1 file changed, 105 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds support to add child devices to gcc as some of the
registers mapped by gcc are used by things like thermal sensors.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
---
drivers/clk/qcom/gcc-msm8960.c | 4
Add thermal zones, tsens and eeprom nodes
Signed-off-by: Rajendra Nayak rna...@codeaurora.org
---
arch/arm64/boot/dts/qcom/msm8916.dtsi | 66 +++
1 file changed, 66 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi
MDP planes can be implemented using different type of HW pipes,
RGB/VIG/DMA pipes for MDP5 and RGB/VG/DMA pipes for MDP4. Each type
of pipe has different HW capabilities such as scaling, color space
conversion, decimation... Add a variable in plane data structure
to specify the difference of each
QUP cores can be attached to a BAM module, which acts as a dma engine for the
QUP core. When DMA with BAM is enabled, the BAM consumer pipe transmitted data
is written to the output FIFO and the BAM producer pipe received data is read
from the input FIFO.
With BAM capabilities, qup-i2c core can
QUP from version 2.1.1 onwards, supports a new format of i2c command tags.
Tag codes instructs the controller to perform a operation like read/write.
This new tagging version supports and is required for adding bam dma
capabilities. V2 tags supports transfer of more than 256 bytes in a single
i2c
The definition of i2c_msg says that
If this is the last message in a group, it is followed by a STOP.
Otherwise it is followed by the next @i2c_msg transaction segment,
beginning with a (repeated) START
So the expectation is that there is no 'STOP' bit inbetween individual
i2c_msg segments with
Signed-off-by: Sricharan R sricha...@codeaurora.org
---
arch/arm/boot/dts/qcom-msm8974.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi
b/arch/arm/boot/dts/qcom-msm8974.dtsi
index f138202..17dcda3 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++
QUP from version 2.1.1 onwards, supports a new format of
i2c command tags. Tag codes instructs the controller to
perform a operation like read/write. This new tagging version
supports bam dma and transfers of more than 256 bytes without 'stop'
in between. Adding the support for the same.
For each
Signed-off-by: Sricharan R sricha...@codeaurora.org
---
arch/arm/boot/dts/qcom-msm8974.dtsi | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi
b/arch/arm/boot/dts/qcom-msm8974.dtsi
index 37b47b5..f138202 100644
---
The qup_i2c_write/read_one functions can be split to have
the common initialization code and function to loop around
the data bytes separately. This way the initialization code
can be reused while adding v2 tags functionality.
Signed-off-by: Sricharan R sricha...@codeaurora.org
---
On Wed, Jul 08, 2015 at 04:56:34PM -0700, Stephen Boyd wrote:
On 06/26/2015 02:50 PM, bj...@kryo.se wrote:
+= EXAMPLE
+The following example shows the SMEM setup for MSM8974, with a main SMEM
region
+at 0xfa0 and an auxiliary region at 0xfc428000:
+
+ reserved-memory {
+
qup_wait_writeready waits only on a output fifo empty event.
Change the same function to accept the event and data length
to wait as parameters. This way the same function can be used for
timeouts in otherplaces as well.
Signed-off-by: Sricharan R sricha...@codeaurora.org
---
dma_alloc_from_coherent uses get_order(size) which makes carve-out
allocations not aligned on order boundaries to fail even though
they are page aligned. So wanted to know why is it required to have
the size aligned on order boundary. Changing it to get_order(PAGE_SIZE)
makes the non aligned
On 06/26/2015 02:50 PM, bj...@kryo.se wrote:
+= EXAMPLE
+The following example shows the SMEM setup for MSM8974, with a main SMEM
region
+at 0xfa0 and an auxiliary region at 0xfc428000:
+
+ reserved-memory {
+ #address-cells = 1;
+ #size-cells = 1;
+
Add chip name and hw-irq number to the trace_irq_handler_entry()
tracepoint. When tracing interrupt events the chip-name and hw-irq
numbers are stable and known in advance. This makes them a better
choice as a filtering criteria for the trace buffer dump. On the
flipside, the os-irq numbers are
On Tue, Jul 7, 2015 at 5:17 PM, Jilai Wang jil...@codeaurora.org wrote:
This change is to add planes which use DMA pipes for MDP5.
are DMA pipes only supporting memory-memory operation, or am I
reading too much into the name DMA? I'm wondering if we need to fix
the possible_crtcs param that
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