Now that the driver is DT adapted, bus_set_iommu gets called
only when on compatible matching. So the driver should not
break multiplatform builds now. So remove the BROKEN config.
Signed-off-by: Sricharan R sricha...@codeaurora.org
---
drivers/iommu/Kconfig | 1 -
1 file changed, 1 deletion(-)
The msm_iommu.c driver currently works based on platform data. A single master
device can be connected to more than one iommu and multiple contexts in each
of the iommu. This association between master and iommus was represented
from platform data using parent/child devices. The master drivers
There are only two functions left in msm_iommu_dev.c. Move it to
msm_iommu.c and delete the file.
Signed-off-by: Sricharan R sricha...@codeaurora.org
---
drivers/iommu/Makefile| 2 +-
drivers/iommu/msm_iommu.c | 163 +
drivers/iommu/msm_iommu_dev.c |
The driver currently works based on platform data. Remove this
and add support for DT. A single master can have multiple ports
connected to more than one iommu.
master
|
|
|
On Wed, Aug 12, 2015 at 03:47:48PM +0100, Sricharan R wrote:
The cacheablity attributes are set when IOMMU_CACHE property
is true. So cachebility is set as either noncached (normal)
or cached (normal WBWA) directly and avoid setting using
tex remap.
Does this IOMMU support the ARMv7 short
On Tue 11 Aug 15:49 PDT 2015, Stephen Boyd wrote:
On 07/08, Rajendra Nayak wrote:
diff --git a/drivers/clk/qcom/gcc-msm8960.c b/drivers/clk/qcom/gcc-msm8960.c
index eb6a4f9..2c80d03 100644
--- a/drivers/clk/qcom/gcc-msm8960.c
+++ b/drivers/clk/qcom/gcc-msm8960.c
@@ -15,6 +15,7 @@
On 08/12/2015 01:18 PM, Bjorn Andersson wrote:
On Tue 11 Aug 15:49 PDT 2015, Stephen Boyd wrote:
On 07/08, Rajendra Nayak wrote:
diff --git a/drivers/clk/qcom/gcc-msm8960.c b/drivers/clk/qcom/gcc-msm8960.c
index eb6a4f9..2c80d03 100644
--- a/drivers/clk/qcom/gcc-msm8960.c
+++
On Wed 12 Aug 14:57 PDT 2015, Stephen Boyd wrote:
On 08/12/2015 01:18 PM, Bjorn Andersson wrote:
On Tue 11 Aug 15:49 PDT 2015, Stephen Boyd wrote:
On 07/08, Rajendra Nayak wrote:
diff --git a/drivers/clk/qcom/gcc-msm8960.c
b/drivers/clk/qcom/gcc-msm8960.c
index eb6a4f9..2c80d03
On 08/11/2015 12:22 PM, Stephen Boyd wrote:
On 08/06, Rajendra Nayak wrote:
+
+static int gdsc_attach(struct generic_pm_domain *domain, struct device *dev)
+{
+ int ret, i = 0, j = 0;
+ struct gdsc *sc = domain_to_gdsc(domain);
+ struct of_phandle_args clkspec;
+ struct
On Wed 05 Aug 09:32 PDT 2015, Lina Iyer wrote:
Hwspinlocks are widely used between processors in an SoC, and also
between elevation levels within in the same processor. QCOM SoC's use
hwspinlock to serialize entry into a low power mode when the context
switches from Linux to secure monitor.
On 08/11/2015 12:23 PM, Stephen Boyd wrote:
On 08/06, Rajendra Nayak wrote:
msm8974 has gcc and mmcc nodes, and apq8084 has a gcc node which
implement gdsc powerdomains. Add the #power-domain-cells property
to them.
Signed-off-by: Rajendra Nayak rna...@codeaurora.org
---
This needs to go
On 11/08/15 23:49, Stephen Boyd wrote:
On 07/08, Rajendra Nayak wrote:
diff --git a/drivers/clk/qcom/gcc-msm8960.c
b/drivers/clk/qcom/gcc-msm8960.c
index eb6a4f9..2c80d03 100644
--- a/drivers/clk/qcom/gcc-msm8960.c
+++ b/drivers/clk/qcom/gcc-msm8960.c
@@ -15,6 +15,7 @@
#include linux/bitops.h
On 11/08/15 23:49, Stephen Boyd wrote:
On 07/08, Rajendra Nayak wrote:
diff --git a/drivers/clk/qcom/gcc-msm8960.c b/drivers/clk/qcom/gcc-msm8960.c
index eb6a4f9..2c80d03 100644
--- a/drivers/clk/qcom/gcc-msm8960.c
+++ b/drivers/clk/qcom/gcc-msm8960.c
@@ -15,6 +15,7 @@
#include
Add support for hardware that support switching both parent clocks and the
divider at the same time. This avoids generating intermediate frequencies
from either the old parent clock and new divider or new parent clock and
old divider combinations.
Signed-off-by: Georgi Djakov
Add a driver for the A53 subsystem PLL, so that we can provide higher
frequency clocks for use by the system.
Signed-off-by: Georgi Djakov georgi.dja...@linaro.org
---
Documentation/devicetree/bindings/clock/qcom,a53cc | 25 +++
drivers/clk/qcom/Kconfig |8 +
From: Stephen Boyd sb...@codeaurora.org
Sometimes clocks can't accept their parent source turning off
while the source is reprogrammed to a different rate. Most
notably CPU clocks require a way to switch away from the current
PLL they're running on, reprogram that PLL to a new rate, and
then
This patchset adds support for the A53 CPU clock and allows scaling
of the CPU frequency on msm8916 based platforms.
Changes since v2 (https://lkml.org/lkml/2015/7/24/526)
* Drop gpll0_vote patch.
* Switch to the new clk_hw_* APIs.
* Rebase to the current clk-next.
Changes since v1
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