On Tue, Dec 08, 2015 at 11:05:36AM -0700, Lina Iyer wrote:
[...]
> On Mon, Dec 07 2015 at 07:53 -0700, Lorenzo Pieralisi wrote:
> >>+/**
> >>+ * of_setup_cpu_domain_topology() - Setup the CPU domains from the CPU
> >>+ * topology node in DT.
> >>+ *
> >>+ * @ops: The PM domain suspend/resume ops
On Thu, Dec 10, 2015 at 1:20 AM, Tomas Winkler wrote:
> Intel uses EFI variables for that on some AOS platforms. There is a
> need for persistent storage abstraction and generalize the reboot
> reasons strings.
Yea. I've been told there isn't any sort of standardized method
On 12/5/2015 3:00 AM, Vinod Koul wrote:
> On Wed, Dec 02, 2015 at 02:04:05PM -0500, Sinan Kaya wrote:
> You are missing the point. Channel can be paused, yes but the descriptor
> is in queue and is not paused. The descriptor running is paused, yes.
> There is subtle difference between
On Thu, Dec 10, 2015 at 6:52 AM, Arnd Bergmann wrote:
> On Wednesday 09 December 2015 17:19:52 John Stultz wrote:
>>
>> If the concern is that since DT is basically ABI, one might not want
>> to have such a wide interface that specifies all the different
>> reasons, I can
On Thu, Dec 10, 2015 at 11:57 AM, One Thousand Gnomes
wrote:
> On Thu, 10 Dec 2015 11:04:03 -0800
> John Stultz wrote:
>> On Thu, Dec 10, 2015 at 1:20 AM, Tomas Winkler wrote:
>> > Second, I wonder why this is submitted under
On 17 November 2015 at 23:37, Lina Iyer wrote:
> From: Marc Titinger
>
> From: Marc Titinger
>
> This patch allows cluster-level idle-states to being soaked in as
> generic domain power states, in order for the domain
On Thu, Dec 10, 2015 at 11:05 AM, Arnd Bergmann wrote:
> On Wednesday 09 December 2015 17:32:02 John Stultz wrote:
>> On Tue, Dec 8, 2015 at 2:07 PM, Bjorn Andersson
>> wrote:
>> > On Tue 08 Dec 13:29 PST 2015, John Stultz wrote:
>> >> diff --git
On Wednesday 09 December 2015 17:32:02 John Stultz wrote:
> On Tue, Dec 8, 2015 at 2:07 PM, Bjorn Andersson
> wrote:
> > On Tue 08 Dec 13:29 PST 2015, John Stultz wrote:
> >> diff --git a/arch/arm/boot/dts/qcom-apq8064-nexus7-flo.dts
> >>
On 12/07/2015 03:30 AM, Adrian Hunter wrote:
> On 04/12/15 17:40, Philip Elcan wrote:
>> On 12/03/2015 09:14 AM, Adrian Hunter wrote:
>>> On 03/12/15 15:48, Philip Elcan wrote:
This allows setting an SDHC controller as non-removable
by using the _RMV method in the ACPI table. It doesn't
On Thu, Dec 10, 2015 at 12:24 PM, Rob Herring wrote:
> The fact that we are using notifiers for reset reason and triggering
> is probably some indication that some infrastructure is needed. But I
> don't think you need to do that here as long as it is all kernel
> internals.
On Thu, Dec 10, 2015 at 12:56 PM, John Stultz wrote:
> On Thu, Dec 10, 2015 at 6:52 AM, Arnd Bergmann wrote:
>> On Wednesday 09 December 2015 17:19:52 John Stultz wrote:
>>>
>>> If the concern is that since DT is basically ABI, one might not want
>>> to
From: Jack Pham
The default value for the 'transceiver select' field of
the PORTSC register may not always be correct. Previously
the phy-msm-usb driver would do this for us, but since
ehci-msm can now be instantiated standalone without any PHY
driver, the register needs to
From: Jack Pham
Currently the EHCI MSM driver has a hard dependency to be created
by an OTG layer, namely the phy-msm-usb driver. In some cases or
board configurations we want to allow the EHCI host to be
instantiated without OTG capability. Instead, relax the dependency
on
From: Jack Pham
Disable the silicon quirk which is normally enabled for HSIC
host mode. This would otherwise prevent low speed devices
from enumerating properly.
Signed-off-by: Jack Pham
Signed-off-by: Timur Tabi
---
From: Jack Pham
Allow the EHCI MSM driver to probe against an ACPI enumerated
device with ID QCOM8040.
Signed-off-by: Jack Pham
Signed-off-by: Timur Tabi
---
drivers/usb/host/ehci-msm.c | 8
1 file changed, 8
On Fri, Nov 6, 2015 at 12:04 AM, Andy Gross wrote:
> This patch sets the AHBMODE to allow for posted data writes. This
> results in higher performance.
>
> Signed-off-by: Andy Gross
I know it's a little late, but ...
Acked-by: Timur Tabi
On Thu, Nov 19, 2015 at 05:19:29PM -0600, Matthew McClintock wrote:
> From: Varadarajan Narayanan
>
> This patch adds support for the global clock controller found on
> the IPQ4019 based devices. This includes UART, I2C, SPI etc.
>
> Signed-off-by: Pradeep Banavathi
On Thu, Nov 19, 2015 at 05:19:28PM -0600, Matthew McClintock wrote:
> From: Varadarajan Narayanan
>
> Add pinctrl driver support for IPQ4019 platform
>
> Signed-off-by: Sricharan R
> Signed-off-by: Mathieu Olivari
>
On Wed, Dec 9, 2015 at 3:53 PM, Russell King - ARM Linux
wrote:
[...]
>> > > dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
>> > > + /*
>> > > + * ensure that the ATU enable has been happaned before accessing
>> > > + * pci configuration/io
Add a device name field in mipi_dsi_device. This name is different from
the actual dev name (which is of the format "hostname.reg"). When the
device is created via DT, this name is set to the modalias string.
In the non-DT case, the driver creating the DSI device provides the
name by populating a
of_mipi_dsi_device_add is used only when CONFIG_OF is enabled. It
currently works if OF support is disabled, but this will change
when we add more functionality to it.
Define the original func if CONFIG_OF is enabled. Define a dummy func
otherwise.
Signed-off-by: Archit Taneja
Simplify the mipi dsi device creation process. device_initialize and
device_add don't need to be called separately when creating
mipi_dsi_device's. Use device_register instead to simplify things.
Create a helper function mipi_dsi_device_new which takes in struct
mipi_dsi_device_info and
A driver calling mipi_dsi_device_new might want to unregister the device
once it's done. It might also require it in an error handling path in
case something didn't go right.
Reviewed-by: Andrzej Hajda
Signed-off-by: Archit Taneja
---
mipi_dsi_devices are inherently aware of their host because they
share a parent-child hierarchy in the device tree.
non-dsi drivers that create dsi device don't have this data. In order to
get this information, they require to a phandle to the dsi host in the
device tree.
Maintain a list of all
We don't check whether a previously registered mipi_dsi_device under the
same host shares the same virtual channel.
Before registering, check if any of the registered devices doesn't
already have the same virtual channel.
This wasn't crucial when all the devices under a host were populated via
We are currently restricted when it comes to supporting DSI on devices
that have a non-DSI control bus. For example, DSI encoder chips are
available in the market that are configured via i2c. Configuring their
registers via DSI bus is either optional or not available at all.
These devices still
On 12/02/2015 07:22 PM, Andy Gross wrote:
> On Wed, Dec 02, 2015 at 06:44:11PM +0200, Stanimir Varbanov wrote:
>> On 12/01/2015 07:23 PM, Andy Gross wrote:
>>> On Tue, Dec 01, 2015 at 11:14:58AM +0200, Stanimir Varbanov wrote:
The pipe fifo size register must instruct the bam hw
how many
This patch set is a resend of the regulator portion of the patches
found at:
https://lkml.org/lkml/2015/9/24/561
This adds support for the PMA8084 regulators found on APQ8084 platforms
and the PM8916 regulators found on MSM8916 platforms. There are no changes from
the version referenced above,
From: Andy Gross
This patch adds all the required nodes to support SMEM on APQ8084
Signed-off-by: Andy Gross
Acked-by: Bjorn Andersson
---
arch/arm/boot/dts/qcom-apq8084.dtsi | 36
From: Andy Gross
This patch adds support and documentation for the PM8916 regulators
found on MSM8916 platforms.
Acked-by: Bjorn Andersson
Signed-off-by: Andy Gross
---
From: Andy Gross
This patch adds support and documentation for the PMA8084 regulators
found on APQ8084 platforms.
Signed-off-by: Andy Gross
Acked-by: Bjorn Andersson
---
On Fri, 11 Dec 2015 09:35:10 +0530 Pratyush Anand wrote:
> On Wed, Dec 9, 2015 at 3:53 PM, Russell King - ARM Linux wrote:
>
> [...]
>
> >> > > dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
> >> > > + /*
> >> > > + * ensure that the ATU enable has been happaned before
From: Andy Gross
This patch adds the nodes necessary to support the SMEM driver on MSM8916
platforms.
Signed-off-by: Andy Gross
Acked-by: Bjorn Andersson
---
arch/arm64/boot/dts/qcom/msm8916.dtsi | 41
This patch set adds the SMEM nodes for the APQ8084 and MSM8916 platforms. These
patches were originally part of:
https://lkml.org/lkml/headers/2015/9/24/561
I split these two patches out because these were the only DTS patches that
required modifications. The rest have been accepted. I
The ARM compiler inserts calls to __aeabi_uidiv() and
__aeabi_idiv() when it needs to perform division on signed and
unsigned integers. If a processor has support for the udiv and
sdiv instructions, the kernel may overwrite the beginning of those
functions with those instructions and a "bx lr" to
On Wed, Dec 09, 2015 at 11:20:45PM +0100, Sebastian Reichel wrote:
> On Wed, Dec 09, 2015 at 09:42:09AM -0800, Tim Bird wrote:
> > There are other switches in the charger block that are not
> > exposed yet. This one handles the the OTG (vbus) charge pathway.
> > Others handle other charge
On Wednesday 09 December 2015 17:19:52 John Stultz wrote:
> On Wed, Dec 9, 2015 at 2:07 AM, Arnd Bergmann wrote:
> > On Tuesday 08 December 2015 16:22:40 John Stultz wrote:
> >> >> diff --git a/arch/arm/boot/dts/qcom-apq8064-nexus7-flo.dts
> >> >>
> []..
>
+Optional properties:
+- qcom,sensor-id: List of sensor instances used in a given SoC. A
TSENS IP can
+have a fixed number of sensors (like 11) but a given SoC can
+use only 5 of these and they might not always the first 5.
They
On Wed, Dec 9, 2015 at 3:08 PM, Rob Herring wrote:
> On Wed, Dec 9, 2015 at 1:59 PM, Bjorn Andersson
> wrote:
>> On Wed 09 Dec 06:36 PST 2015, Rob Herring wrote:
>>
>>> On Wed, Dec 9, 2015 at 6:55 AM, Tim Bird wrote:
>>>
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