Re: [PATCH v5 1/5] PCI: designware: ensure ATU is enabled before IO/conf space accesses

On 12/18/2015 04:41 PM, Pratyush Anand wrote: > On Fri, Dec 18, 2015 at 6:08 PM, Stanimir Varbanov > <stanimir.varba...@linaro.org> wrote: >> There is no guarantees that enabling ATU will hit the hardware >> immediately, and subsequent accesses to configuration / IO sp

Re: [PATCH v4 5/5] ARM: dts: ifc6410: enable pcie dt node for this board

On 12/17/2015 11:55 PM, Bjorn Andersson wrote: > On Thu 03 Dec 05:35 PST 2015, Stanimir Varbanov wrote: > >> Enable pcie dt node and fill pcie dt node with regulator, pinctrl >> and reset gpio, to use the pcie on the ifc6410 board. >> >> Signed-off-by: Sta

[PATCH v5 2/5] DT: PCI: qcom: Document PCIe devicetree bindings

From: Stanimir Varbanov <svarba...@mm-sol.com> Document Qualcomm PCIe driver devicetree bindings. Signed-off-by: Stanimir Varbanov <svarba...@mm-sol.com> Signed-off-by: Stanimir Varbanov <stanimir.varba...@linaro.org> Acked-by: Rob Herring <r...@kernel.org> --- .../devi

[PATCH v5 5/5] ARM: dts: ifc6410: enable pcie dt node for this board

Enable pcie dt node and fill pcie dt node with regulator, pinctrl and reset gpio, to use the pcie on the ifc6410 board. Signed-off-by: Stanimir Varbanov <stanimir.varba...@linaro.org> --- arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 26 ++ 1 file changed, 26 inse

[PATCH v5 4/5] ARM: dts: apq8064: add pcie devicetree node

Add the pcie dt node so that it can probe and used. Signed-off-by: Stanimir Varbanov <stanimir.varba...@linaro.org> --- arch/arm/boot/dts/qcom-apq8064.dtsi | 36 +++ 1 file changed, 36 insertions(+) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/ar

[PATCH v5 0/5] Qualcomm PCIe driver and designware fixes

. - in 5/5 - addressed a comment from Bjorn Andersson about regulator label duplication. Comments are welcome! The previous v4 of the patch set can be found at [1]. regards, Stan [1] https://lkml.org/lkml/2015/12/3/370 Stanimir Varbanov (5): PCI: designware: ensure ATU is enabled before IO

[PATCH v5 1/5] PCI: designware: ensure ATU is enabled before IO/conf space accesses

, and reading configuration space for particular PCI device on the bus returns zero aka no device. Signed-off-by: Stanimir Varbanov <stanimir.varba...@linaro.org> --- drivers/pci/host/pcie-designware.c |7 +++ 1 file changed, 7 insertions(+) diff --git a/drivers/pci/host/pcie-designwar

[PATCH v5 3/5] PCI: qcom: Add Qualcomm PCIe controller driver

From: Stanimir Varbanov <svarba...@mm-sol.com> The PCIe driver reuse the Designware common code for host and MSI initialization, and also program the Qualcomm application specific registers. Signed-off-by: Stanimir Varbanov <svarba...@mm-sol.com> Signed-off-by: Stanimir Varbanov <

Re: [PATCH v4 3/5] PCI: qcom: Add Qualcomm PCIe controller driver

Bjorn, thanks for the comments! On 12/16/2015 11:53 PM, Bjorn Helgaas wrote: > On Thu, Dec 03, 2015 at 03:35:22PM +0200, Stanimir Varbanov wrote: >> From: Stanimir Varbanov <svarba...@mm-sol.com> >> >> The PCIe driver reuse the Designware common code for host >>

Re: [PATCH v4 1/5] PCI: designware: add memory barrier after enabling region

On 12/11/2015 06:05 AM, Pratyush Anand wrote: > On Wed, Dec 9, 2015 at 3:53 PM, Russell King - ARM Linux > wrote: > > [...] > > dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2); > + /* > + * ensure that the ATU enable has been happaned

Re: [PATCH v4 3/5] PCI: qcom: Add Qualcomm PCIe controller driver

On 12/03/2015 03:35 PM, Stanimir Varbanov wrote: > From: Stanimir Varbanov <svarba...@mm-sol.com> > > The PCIe driver reuse the Designware common code for host > and MSI initialization, and also program the Qualcomm > application specific registers. > > Signed-off-by

Re: [PATCH 3/4] dmaengine: qcom_bam_dma: use correct pipe FIFO size

On 12/02/2015 07:22 PM, Andy Gross wrote: > On Wed, Dec 02, 2015 at 06:44:11PM +0200, Stanimir Varbanov wrote: >> On 12/01/2015 07:23 PM, Andy Gross wrote: >>> On Tue, Dec 01, 2015 at 11:14:58AM +0200, Stanimir Varbanov wrote: >>>> The pipe fifo size register must ins

Re: [PATCH v4 1/5] PCI: designware: add memory barrier after enabling region

On 12/09/2015 11:52 AM, Arnd Bergmann wrote: > On Wednesday 09 December 2015 10:10:05 Pratyush Anand wrote: >> On Tue, Dec 8, 2015 at 2:31 PM, Stanimir Varbanov >>>> Signed-off-by: Stanimir Varbanov <stanimir.varba...@linaro.org> >>>> --- >>

Re: [PATCH v4 1/5] PCI: designware: add memory barrier after enabling region

On 12/03/2015 03:35 PM, Stanimir Varbanov wrote: > Add 'write memory' barrier after enable region in PCIE_ATU_CR2 > register. The barrier is needed to ensure that the region enable > request has been reached it's destination at time when we > read/write to PCI configuration space.

[PATCH v4 3/5] PCI: qcom: Add Qualcomm PCIe controller driver

From: Stanimir Varbanov <svarba...@mm-sol.com> The PCIe driver reuse the Designware common code for host and MSI initialization, and also program the Qualcomm application specific registers. Signed-off-by: Stanimir Varbanov <svarba...@mm-sol.com> Signed-off-by: Stanimir Varbanov <

[PATCH v4 4/5] ARM: dts: apq8064: add pcie devicetree node

Add the pcie dt node so that it can probe and used. Signed-off-by: Stanimir Varbanov <stanimir.varba...@linaro.org> --- arch/arm/boot/dts/qcom-apq8064.dtsi | 36 +++ 1 file changed, 36 insertions(+) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/ar

[PATCH v4 5/5] ARM: dts: ifc6410: enable pcie dt node for this board

Enable pcie dt node and fill pcie dt node with regulator, pinctrl and reset gpio, to use the pcie on the ifc6410 board. Signed-off-by: Stanimir Varbanov <stanimir.varba...@linaro.org> --- arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 26 ++ 1 file changed, 26 inse

[PATCH v4 1/5] PCI: designware: add memory barrier after enabling region

is not reliable, and reading configuration space for particular PCI device on the bus returns zero aka no device. Signed-off-by: Stanimir Varbanov <stanimir.varba...@linaro.org> --- drivers/pci/host/pcie-designware.c |5 + 1 file changed, 5 insertions(+) diff --git a/drivers/pci/hos

[PATCH v4 2/5] DT: PCI: qcom: Document PCIe devicetree bindings

From: Stanimir Varbanov <svarba...@mm-sol.com> Document Qualcomm PCIe driver devicetree bindings. Signed-off-by: Stanimir Varbanov <svarba...@mm-sol.com> Signed-off-by: Stanimir Varbanov <stanimir.varba...@linaro.org> --- .../devicetree/bindings/pci/qcom,pcie.t

[PATCH v4 0/5] Qualcomm PCIe driver and designware fixes

Hi, Here is v4, comments from Bjorn and Rob have been addressed. The previous version can be found at [1]. regards, Stan [1] https://lkml.org/lkml/2015/11/23/114 Stanimir Varbanov (5): PCI: designware: add memory barrier after enabling region DT: PCI: qcom: Document PCIe devicetree

Re: [PATCH 2/4] dmaengine: qcom_bam_dma: clear BAM interrupt only if it is rised

On 12/02/2015 03:05 PM, Arnd Bergmann wrote: > On Wednesday 02 December 2015 14:56:57 Stanimir Varbanov wrote: >> On 12/01/2015 12:29 PM, Arnd Bergmann wrote: >>> On Tuesday 01 December 2015 11:14:57 Stanimir Varbanov wrote: >>>> + if (srcs & BAM_IR

Re: [PATCH 3/4] dmaengine: qcom_bam_dma: use correct pipe FIFO size

On 12/01/2015 07:23 PM, Andy Gross wrote: > On Tue, Dec 01, 2015 at 11:14:58AM +0200, Stanimir Varbanov wrote: >> The pipe fifo size register must instruct the bam hw >> how many hw descriptors can be pushed to fifo. Currently >> we isntruct the hw with 32KBy

Re: [PATCH 2/4] dmaengine: qcom_bam_dma: clear BAM interrupt only if it is rised

On 12/01/2015 12:29 PM, Arnd Bergmann wrote: > On Tuesday 01 December 2015 11:14:57 Stanimir Varbanov wrote: >> + if (srcs & BAM_IRQ) { >> clr_mask = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_STTS)); >> >> - /* don't allow reorder of

[PATCH 0/4] bam dma fixes and one dt extension

for peripherals which BAM is remotely controlled by other execution environment. All patches has been tested on db410c board with apq8016. Comments are welcome! regards, Stan Stanimir Varbanov (4): dmaengine: qcom_bam_dma: fix dma free memory on remove dmaengine: qcom_bam_dma: clear BAM interrupt

[PATCH 3/4] dmaengine: qcom_bam_dma: use correct pipe FIFO size

the correct fifo size in BAM_P_FIFO_SIZES register i.e. 32K - 8. Signed-off-by: Stanimir Varbanov <stanimir.varba...@linaro.org> --- drivers/dma/qcom_bam_dma.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/dma/qcom_bam_dma.c b/drivers/dma/qcom_bam_dma.c index 0f06f3

[PATCH 1/4] dmaengine: qcom_bam_dma: fix dma free memory on remove

freed memory. Signed-off-by: Stanimir Varbanov <stanimir.varba...@linaro.org> --- drivers/dma/qcom_bam_dma.c |3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/dma/qcom_bam_dma.c b/drivers/dma/qcom_bam_dma.c index 5a250cdc8376..dc9da477eb69 100644 --- a/drivers/dma/qcom_bam

Re: [PATCH v3 3/6] DT: PCI: qcom: Document PCIe devicetree bindings

Bjorn, thanks for the comments! On 11/23/2015 08:13 PM, Bjorn Andersson wrote: > On Mon 23 Nov 01:29 PST 2015, Stanimir Varbanov wrote: > >> From: Stanimir Varbanov <svarba...@mm-sol.com> >> >> Document Qualcomm PCIe driver devicetree bindings. >> >>

[PATCH] PCI: designware: remove wrong io_base assignment

e_resources() to parse DT") Reviewed-by: Arnd Bergmann <a...@arndb.de> Signed-off-by: Stanimir Varbanov <stanimir.varba...@linaro.org> --- drivers/pci/host/pcie-designware.c |1 - 1 file changed, 1 deletion(-) diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/

Re: [PATCH v3 3/6] DT: PCI: qcom: Document PCIe devicetree bindings

Thanks for the comments! On 11/24/2015 01:17 AM, Rob Herring wrote: > On Mon, Nov 23, 2015 at 11:29:00AM +0200, Stanimir Varbanov wrote: >> From: Stanimir Varbanov <svarba...@mm-sol.com> >> >> Document Qualcomm PCIe driver devicetree bindings. >> >> Signed-

Re: [PATCH v3 1/6] PCI: designware: remove wrong io_base assignment

On 11/23/2015 06:40 PM, Arnd Bergmann wrote: > On Monday 23 November 2015 18:23:47 Stanimir Varbanov wrote: >>>> >>>> Fixes: 0021d22b73d6 ("PCI: designware: Use >>>> of_pci_get_host_bridge_resources() >>>> to parse DT") >>

[PATCH v3 5/6] ARM: dts: apq8064: add pcie devicetree node

Add the pcie dt node so that it can probe and used. Signed-off-by: Stanimir Varbanov <stanimir.varba...@linaro.org> --- arch/arm/boot/dts/qcom-apq8064.dtsi | 36 +++ 1 file changed, 36 insertions(+) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/ar

[PATCH v3 3/6] DT: PCI: qcom: Document PCIe devicetree bindings

From: Stanimir Varbanov <svarba...@mm-sol.com> Document Qualcomm PCIe driver devicetree bindings. Signed-off-by: Stanimir Varbanov <svarba...@mm-sol.com> Signed-off-by: Stanimir Varbanov <stanimir.varba...@linaro.org> --- .../devicetree/bindings/pci/qcom,pcie.t

[PATCH v3 4/6] PCI: qcom: Add Qualcomm PCIe controller driver

From: Stanimir Varbanov <svarba...@mm-sol.com> The PCIe driver reuse the Designware common code for host and MSI initialization, and also program the Qualcomm application specific registers. Signed-off-by: Stanimir Varbanov <svarba...@mm-sol.com> Signed-off-by: Stanimir Varbanov <

[PATCH v3 2/6] PCI: designware: add memory barrier after enabling region

is not reliable, and reading configuration space for particular PCI device on the bus returns zero aka no device. Signed-off-by: Stanimir Varbanov <stanimir.varba...@linaro.org> --- drivers/pci/host/pcie-designware.c |5 + 1 file changed, 5 insertions(+) diff --git a/drivers/pci/hos

[PATCH v3 0/6] Qualcomm PCIe driver and designware fixes

Stanimir Varbanov (6): PCI: designware: remove wrong io_base assignment PCI: designware: add memory barrier after enabling region DT: PCI: qcom: Document PCIe devicetree bindings PCI: qcom: Add Qualcomm PCIe controller driver ARM: dts: apq8064: add pcie devicetree node ARM: dts: ifc6410

[PATCH v3 1/6] PCI: designware: remove wrong io_base assignment

The io_base is used to keep the cpu physical address parsed from ranges dt property. After issue pci_remap_iospace the io_base has been assigned with io->start, which is not correct cause io->start is a PCI bus address. Signed-off-by: Stanimir Varbanov <stanimir.varba...@linaro.org>

Re: [PATCH v3 1/6] PCI: designware: remove wrong io_base assignment

On 11/23/2015 12:27 PM, Gabriele Paoloni wrote: > Hi Stanimir, Many Thanks for this fix > >> -Original Message- >> From: linux-kernel-ow...@vger.kernel.org [mailto:linux-kernel- >> ow...@vger.kernel.org] On Behalf Of Arnd Bergmann >> Sent: 23 November 2015

Re: [PATCH v3 2/6] PCI: designware: add memory barrier after enabling region

On 11/23/2015 01:27 PM, Russell King - ARM Linux wrote: > On Mon, Nov 23, 2015 at 11:28:59AM +0200, Stanimir Varbanov wrote: >> Add 'write memory' barrier after enable region in PCIE_ATU_CR2 >> register. The barrier is needed to ensure that the region enable >> request

Re: [PATCH v2 4/5] PCI: qcom: Add Qualcomm PCIe controller driver

Hi Bjorn, On 11/06/2015 10:50 PM, Bjorn Andersson wrote: > On Mon 04 May 05:42 PDT 2015, Stanimir Varbanov wrote: > >> The PCIe driver reuse the Designware common code for host >> and MSI initialization, and also program the Qualcomm >> application specific register

Re: [PATCH] soc/qcom: add OCMEM driver

Hi Rob, On 10/13/2015 12:45 AM, Rob Clark wrote: > The OCMEM driver handles allocation and configuration of the On Chip > MEMory that is present on some snapdragon devices. > > Devices which have OCMEM do not have GMEM inside the gpu core, so the > gpu must instead use OCMEM to be functional.

Re: [PATCH] soc/qcom: add OCMEM driver

Hi Rob, > + > +struct ocmem_config { > + uint8_t num_regions; u8 > + uint32_t macro_size; u32 > +static const struct ocmem_config ocmem_8974_config = { > + .num_regions = 3, .macro_size = SZ_128K, > +}; > + > +static const struct of_device_id ocmem_dt_match[] = { > + {

Re: [PATCH 6/6] drm/msm: add OCMEM driver

On 09/30/2015 02:45 PM, Rob Clark wrote: > On Wed, Sep 30, 2015 at 7:31 AM, Rob Clark <robdcl...@gmail.com> wrote: >> On Wed, Sep 30, 2015 at 3:51 AM, Stanimir Varbanov >> <stanimir.varba...@linaro.org> wrote: >>> Hi Rob, >>> >>> Thanks fo

Re: [PATCH 6/6] drm/msm: add OCMEM driver

Hi Rob, Thanks for your work. On 09/29/2015 10:48 PM, Rob Clark wrote: > For now, since the GPU is the only upstream consumer, just stuff this > into drm/msm. Eventually if we have other consumers, we'll have to As the video encoder/decoder driver (vidc) for apq8084 && msm8974 also use the

Re: [PATCH 1/4] dt-binding: gpio: Add Qualcomm SMSM device tree documentation

On 08/27/2015 08:37 PM, Bjorn Andersson wrote: > This documents a device tree binding for exposing the Qualcomm Shared > Memory State Machine as a set of gpio- and interrupt-controllers. > > Signed-off-by: Bjorn Andersson > --- >

Re: [PATCH v2] soc: qcom: smd: Use correct remote processor ID

On 08/26/2015 10:42 PM, Andy Gross wrote: This patch fixes SMEM addressing issues when remote processors need to use secure SMEM partitions. Signed-off-by: Andy Gross agr...@codeaurora.org --- .../devicetree/bindings/soc/qcom/qcom,smd.txt |6 ++ drivers/soc/qcom/smd.c

[PATCH] arm64: dts: qcom: Add RNG device tree node

Adds rng device tree node for msm8916 SoCs. Signed-off-by: Stanimir Varbanov stanimir.varba...@linaro.org --- arch/arm64/boot/dts/qcom/msm8916.dtsi |7 +++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index

Re: [PATCH v7 12/13] clk: qcom: gdsc: Add GDSCs in apq8084 MMCC

snip +static struct gdsc venus0_gdsc = { + .gdscr = 0x1024, + .pd = { + .name = venus0, + }, + .pwrsts = PWRSTS_OFF_ON, + .con_ids = { NULL }, +}; + Rajendra, according to downstream kernel apq8084 has second instance of gdsc i.e. venus1_gdsc, is that

Re: drm: msm: run into issues

On 07/23/2015 06:59 PM, Rob Clark wrote: On Thu, Jul 23, 2015 at 5:02 AM, Stanimir Varbanov stanimir.varba...@linaro.org wrote: Hi Rob, I run into issues with msm drm driver while implementing a test application which use v4l2 vidc (venus) decoder driver to decode videos and msm drm driver

Re: [PATCH v6 03/13] clk: qcom: gdsc: Use PM clocks to control gdsc clocks

On 07/23/2015 11:34 AM, Rajendra Nayak wrote: On 07/23/2015 06:31 AM, Stephen Boyd wrote: On 07/22/2015 12:10 AM, Rajendra Nayak wrote: @@ -104,6 +105,37 @@ static int gdsc_disable(struct generic_pm_domain *domain) return gdsc_toggle_logic(sc, false); } +static int

Re: [PATCH v2 2/5] phy: qcom: Add Qualcomm PCIe PHY

On 05/20/2015 04:23 PM, Bjorn Helgaas wrote: On Wed, May 20, 2015 at 8:08 AM, Kishon Vijay Abraham I kis...@ti.com wrote: Hi Bjorn, On Wednesday 20 May 2015 04:11 AM, Bjorn Helgaas wrote: On Mon, May 04, 2015 at 06:24:10PM +0300, Stanimir Varbanov wrote: On 05/04/2015 05:35 PM, Kishon

Re: [PATCH v2 2/6] clk: qcom: gdsc: Prepare common clk probe to register gdscs

Hi Rajendra, Thanks for the patch! On 03/19/2015 10:02 AM, Rajendra Nayak wrote: The common clk probe registers a clk provider and a reset controller. Update it to register a genpd provider using the gdsc data provided by each platform. Signed-off-by: Rajendra Nayak rna...@codeaurora.org

Re: [PATCH 1/2] DT: arm64: msm8916: add all SPI DT nodes

On 03/18/2015 02:26 PM, Srinivas Kandagatla wrote: On 17/03/15 16:25, Stanimir Varbanov wrote: + +spi4_sleep: spi4_sleep { +pinmux { +function = gpio; +pins = gpio12, gpio13, gpio14, gpio15

Re: [PATCH v5 2/4] arm64: dts: Add Qualcomm MSM8916 SoC and evaluation board dts

On 03/13/2015 06:06 PM, Kumar Gala wrote: Add initial device tree support for Qualcomm MSM8916 SoC and MTP8916 evaluation board. At the current time we only boot up a single processor. Signed-off-by: Kumar Gala ga...@codeaurora.org --- v5: * killed use of skeleton, moved to addr/size

Re: [PATCH 5/6] dts: msm8974: Add blsp2_bam dma node

On 03/13/2015 07:49 PM, Sricharan R wrote: Signed-off-by: Sricharan R sricha...@codeaurora.org --- arch/arm/boot/dts/qcom-msm8974.dtsi | 10 ++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index

[PATCH 1/2] DT: arm64: msm8916: add all SPI DT nodes

Add SPI DT nodes for the SoC. Every SPI DT node has reference to blsp dma node with relevant dma channels and appropriate pinctrl nodes to configure SPI pins. Signed-off-by: Stanimir Varbanov stanimir.varba...@linaro.org --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 317

[PATCH 2/2] DT: arm64: msm8916-mtp: enable spi3

This enable spi3 on msm8916 mtp board Signed-off-by: Stanimir Varbanov stanimir.varba...@linaro.org --- arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi |8 1 files changed, 8 insertions(+), 0 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi b/arch/arm64/boot/dts/qcom

Re: [PATCH 0/6] Add support for QCOM GDSCs

On 03/02/2015 09:02 AM, Rajendra Nayak wrote: GDSCs (Global Distributed Switch Controllers) control switches that supply power to an on-chip power domain and hence can be programmed in SW to safely power collapse and restore power to the respective PDs. They are part of a considerable number

Re: [PATCH 2/6] clk: qcom: gdsc: Prepare common clk probe to register gdscs

On 03/02/2015 09:02 AM, Rajendra Nayak wrote: The common clk probe registers a clk provider and a reset controller. Update it to register a genpd provider using the gdsc data provided by each platform. Signed-off-by: Rajendra Nayak rna...@codeaurora.org --- drivers/clk/qcom/common.c | 27

Re: [PATCH 1/6] clk: qcom: Add support for GDSCs

On 03/02/2015 09:02 AM, Rajendra Nayak wrote: From: Stephen Boyd sb...@codeaurora.org GDSCs (Global Distributed Switch Controllers) are responsible for safely collapsing and restoring power to peripherals in the SoC. These are best modelled as power domains using genpd and given the

Re: [PATCH] dmaengine: bam-dma: fill slave directions bit mask

On 03/04/2015 09:44 PM, Andy Gross wrote: On Wed, Mar 04, 2015 at 09:32:13PM +0530, Vinod Koul wrote: On Wed, Mar 04, 2015 at 05:25:10PM +0200, Stanimir Varbanov wrote: This will avoid warning during async device registration. Signed-off-by: Stanimir Varbanov stanimir.varba...@linaro.org

[PATCH] dmaengine: bam-dma: fill slave directions bit mask

This will avoid warning during async device registration. Signed-off-by: Stanimir Varbanov stanimir.varba...@linaro.org --- drivers/dma/qcom_bam_dma.c |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/drivers/dma/qcom_bam_dma.c b/drivers/dma/qcom_bam_dma.c index c3113e3

Re: [PATCH v3 3/3] pinctrl: qcom: Add msm8916 pinctrl driver

On 03/02/2015 04:40 PM, Linus Walleij wrote: On Wed, Feb 4, 2015 at 3:39 PM, Stanimir Varbanov svarba...@mm-sol.com wrote: On 02/03/2015 06:47 PM, Andy Gross wrote: On Fri, Jan 30, 2015 at 12:04:01PM +0200, Stanimir Varbanov wrote: From: Joonwoo Park joonw...@codeaurora.org Add initial

Re: [PATCH v3] spi: qup: Add DMA capabilities

On 03/04/2015 10:38 AM, Ivan T. Ivanov wrote: Hi Stan, It looks good now, except it doesn't apply and two small issues below: snip + + /* set DMA parameters */ + rx_conf-direction = DMA_DEV_TO_MEM; + rx_conf-device_fc = 1; Strictly speeching this is a bool not

[PATCH v4] spi: qup: Add DMA capabilities

...@codeaurora.org Signed-off-by: Stanimir Varbanov stanimir.varba...@linaro.org --- v3 - v4 - correct error path when setting to reset state fails Third version can be found at https://lkml.org/lkml/2015/2/27/369 v2 - v3 - now using one dma done callback on rx channel if bidirectional transfer

[PATCH v2 2/2] pinctrl: qcom: handle input-enable pinconf property

This enables support of 'input-enable' pinconf generic property in the pinctrl driver. Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com --- drivers/pinctrl/qcom/pinctrl-msm.c | 11 +++ 1 files changed, 11 insertions(+), 0 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl

[PATCH v2 0/2] pinctrl: qcom: enable generic pinconf and input-enable

From: Stanimir Varbanov stanimir.varba...@linaro.org v1 - v2 - addressed a review comment from Linus about returned error in 1/2 - added Reviewed-by tag in 1/2 - 2/2 has no changes First version of the patchset can be found at https://lkml.org/lkml/2015/1/30/202

[PATCH v2 1/2] pinctrl: qcom: enable generic pinconf

This makes the pinctrl driver to use the generic pinconf interface. Mainly it gives us a way to use debugfs to dump group configurations. Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com Reviewed-by: Linus Walleij linus.wall...@linaro.org --- drivers/pinctrl/qcom/pinctrl-msm.c |6

[PATCH v3] spi: qup: Add DMA capabilities

...@codeaurora.org Signed-off-by: Stanimir Varbanov stanimir.varba...@linaro.org --- v2 - v3 - now using one dma done callback on rx channel if bidirectional transfer and on tx channel if only transmit transfer - rearranged the spi_qup_transfer_one() in order to reuse wait for completion

Re: [PATCH v2] spi: qup: Add DMA capabilities

On 02/26/2015 04:33 AM, Mark Brown wrote: On Tue, Feb 24, 2015 at 06:08:54PM +0200, Stanimir Varbanov wrote: yes, there is a potential race between atomic_inc and dma callback. I reordered these calls to save few checks, and now it returns to me. I imagine few options here: - reorder

Re: [PATCH 06/12] ARM: DT: apq8064: add pci support in CM QS600

On 02/23/2015 01:43 PM, Srinivas Kandagatla wrote: Hi Kumar, Sorry, I should have dropped this patch.. PCIE is still not in the mainline.. :-) Srini, Does it possible to reuse the driver which I'm trying to upstream at [1] ? I'm planing to send v2 soon. [1]

[PATCH v2] spi: qup: Add DMA capabilities

...@codeaurora.org Signed-off-by: Stanimir Varbanov stanimir.varba...@linaro.org --- This is reworked version with comments addressed - use SPI core DMA mapping code - implemented .can_dma callback - use dmaengine api's to account deferred_probe First version can be found at [1]. [1] https://lkml.org

Re: [PATCH v2] spi: qup: Add DMA capabilities

On 02/24/2015 03:56 PM, Mark Brown wrote: On Tue, Feb 24, 2015 at 03:00:03PM +0200, Stanimir Varbanov wrote: +static void spi_qup_dma_done(void *data) +{ +struct spi_qup *qup = data; + +if (atomic_dec_and_test(qup-dma_outstanding)) +complete(qup-done); +} I'm

[PATCH] dmaengine: qcom_bam_dma: fix wrong register offsets

The commit fb93f520e (dmaengine: qcom_bam_dma: Generalize BAM register offset calculations) wrongly populated base offsets for event registers for bam v1.4. Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com --- drivers/dma/qcom_bam_dma.c |6 +++--- 1 files changed, 3 insertions(+), 3

Re: [PATCH] dmaengine: qcom_bam_dma: Add support for BAM v1.7.0

--- Looks good. Reviewed-by: Andy Gross agr...@codeaurora.org Reviewed-by: Stanimir Varbanov svarba...@mm-sol.com Vinod, is that one OK with you? If so could you merge it in your tree. regards, Stan -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body

Re: [PATCH] spmi: pmic_arb: enable build on arm64 platforms

On 02/03/2015 10:42 PM, Paul Bolle wrote: On Tue, 2015-02-03 at 15:50 +0200, Stanimir Varbanov wrote: This enables pmic arbiter driver to be build on arm64 platforms. Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com --- drivers/spmi/Kconfig |2 +- 1 files changed, 1 insertions

Re: [PATCH] spmi: pmic_arb: enable build on arm64 platforms

On 02/04/2015 05:14 PM, Paul Bolle wrote: On Wed, 2015-02-04 at 17:05 +0200, Stanimir Varbanov wrote: On 02/03/2015 10:42 PM, Paul Bolle wrote: On Tue, 2015-02-03 at 15:50 +0200, Stanimir Varbanov wrote: diff --git a/drivers/spmi/Kconfig b/drivers/spmi/Kconfig index bf1295e..115348c 100644

[PATCH] spmi: pmic_arb: enable build on arm64 platforms

This enables pmic arbiter driver to be build on arm64 platforms. Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com --- drivers/spmi/Kconfig |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/spmi/Kconfig b/drivers/spmi/Kconfig index bf1295e..115348c 100644

Re: [PATCH V2 2/2] spmi: pmic_arb: add support for hw version 2

Hi Gilad, Thanks for the patch. On 01/31/2015 02:46 AM, Gilad Avidov wrote: Qualcomm PMIC Arbiter version-2 changes from version-1 are: - Some different register offsets. - New channel register space, one per PMIC peripheral (ppid). All tx traffic uses these channels. - New observer

Re: [PATCH v4] thermal: Add QPNP PMIC temperature alarm driver

On 02/02/2015 05:19 PM, Ivan T. Ivanov wrote: Add support for the temperature alarm peripheral found inside Qualcomm plug-and-play (QPNP) PMIC chips. The temperature alarm peripheral outputs a pulse on an interrupt line whenever the thermal over temperature stage value changes. Register a

[PATCH 1/3] pinctrl: qcom: delete pin_config_get/set pinconf operations

The .pin_config_get/set operation are not supported in qcom pinctrl driver. As the pinconf core is smart enough it doesn't complain about that. Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com --- drivers/pinctrl/qcom/pinctrl-msm.c | 17 - 1 files changed, 0 insertions

[PATCH v3 2/3] DT: pinctrl: Document Qualcomm MSM8916 pinctrl binding

Adds devicetree binding documentation. Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com Reviewed-by: Bjorn Andersson bjorn.anders...@sonymobile.com --- .../bindings/pinctrl/qcom,msm8916-pinctrl.txt | 186 1 files changed, 186 insertions(+), 0 deletions(-) create

[PATCH 2/3] pinctrl: qcom: enable generic pinconf

This makes the pinctrl driver to use the generic pinconf interface. Mainly it gives us a way to use debugfs to dump group configurations. Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com --- drivers/pinctrl/qcom/pinctrl-msm.c |4 +--- 1 files changed, 1 insertions(+), 3 deletions

[PATCH v3 0/3] pinctrl: Qualcomm msm8916 pinctrl driver

are welcome! regards, Stan Joonwoo Park (2): pinctrl: qcom: increase variable size for register offsets pinctrl: qcom: Add msm8916 pinctrl driver Stanimir Varbanov (1): DT: pinctrl: Document Qualcomm MSM8916 pinctrl binding .../bindings/pinctrl/qcom,msm8916-pinctrl.txt | 186

[PATCH v3 1/3] pinctrl: qcom: increase variable size for register offsets

From: Joonwoo Park joonw...@codeaurora.org On newer TLMM hardware blocks the registers are spread and we need an offsets upper than 16 bits to address them. Increase the register offset variables to 32 bits size. Signed-off-by: Joonwoo Park joonw...@codeaurora.org Signed-off-by: Stanimir

Re: [PATCH 3/3] pinctrl: qcom: Add msm8916 pinctrl driver

Hi Andy, On 01/29/2015 01:18 AM, Andy Gross wrote: On Tue, Jan 20, 2015 at 11:17:56AM +0200, Stanimir Varbanov wrote: snip +MSM_MUX_blsp1_spi, +MSM_MUX_blsp2_spi, +MSM_MUX_blsp3_spi, The above three need to be renamed to blsp_spiX_csX to denote which SPI and chip select

Re: [PATCH 1/6] soc: qcom: gsbi: Add support for ADM CRCI muxing

Hi Andy, On 01/28/2015 12:10 AM, Andy Gross wrote: This patch adds automatic configuration for the ADM CRCI muxing required to support DMA operations for GSBI clients. The GSBI mode and instance determine the correct TCSR ADM CRCI MUX value that must be programmed so that the DMA works

[PATCH v2 2/3] DT: pinctrl: Document Qualcomm MSM8916 pinctrl binding

Adds devicetree binding documentation. Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com Reviewed-by: Bjorn Andersson bjorn.anders...@sonymobile.com --- .../bindings/pinctrl/qcom,msm8916-pinctrl.txt | 186 1 files changed, 186 insertions(+), 0 deletions(-) create

[PATCH v2 0/3] pinctrl: Qualcomm msm8916 pinctrl driver

pinctrl driver Stanimir Varbanov (1): DT: pinctrl: Document Qualcomm MSM8916 pinctrl binding .../bindings/pinctrl/qcom,msm8916-pinctrl.txt | 186 +++ drivers/pinctrl/qcom/Kconfig |8 + drivers/pinctrl/qcom/Makefile |1 + drivers/pinctrl

[PATCH v2 1/3] pinctrl: qcom: increase variable size for register offsets

From: Joonwoo Park joonw...@codeaurora.org On newer TLMM hardware blocks the registers are spread and we need an offsets upper than 16 bits to address them. Increase the register offset variables to 32 bits size. Signed-off-by: Joonwoo Park joonw...@codeaurora.org Signed-off-by: Stanimir

[PATCH v2 3/3] pinctrl: qcom: Add msm8916 pinctrl driver

From: Joonwoo Park joonw...@codeaurora.org Add initial pinctrl driver to support pin configuration with pinctrl framework for msm8916. Signed-off-by: Joonwoo Park joonw...@codeaurora.org Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com Reviewed-by: Bjorn Andersson bjorn.anders

Re: [PATCH] pinctrl: qcom: enable generic support and input-enable pinctrl conf

Hi Stephen, Thanks for the comments! On 01/27/2015 03:18 AM, Stephen Boyd wrote: On 01/26/15 08:24, Stanimir Varbanov wrote: Enables generic pinconf support and add handling for 'input-enable' pinconf property. Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com --- drivers/pinctrl

[PATCH] pinctrl: qcom: enable generic support and input-enable pinctrl conf

Enables generic pinconf support and add handling for 'input-enable' pinconf property. Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com --- drivers/pinctrl/qcom/pinctrl-msm.c | 17 - 1 files changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/qcom

Re: [PATCH] spmi: pmic_arb: add support for hw version 2

Hi Gilad, snip -/* Non-data command */ -static int pmic_arb_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid) +static int +pmic_arb_non_data_cmd_v1(struct spmi_controller *ctrl, u8 opc, u8 sid) { struct spmi_pmic_arb_dev *pmic_arb = spmi_controller_get_drvdata(ctrl);

Re: [PATCH] spmi: pmic_arb: add support for hw version 2

Hi Gilad, snip /* Interrupt Controller */ #define SPMI_PIC_OWNER_ACC_STATUS(M, N) (0x + ((32 * (M)) + (4 * (N It looks like these macros would change too, but nothing has been done here. Interrupts haven't been tested? Stephen is right, the irq related operations are not

Re: [PATCH 2/5] phy: qcom: Add Qualcomm PCIe PHY

Hi Kishon, Thanks for the comments! On 01/21/2015 11:11 AM, Kishon Vijay Abraham I wrote: Hi, On Friday 12 December 2014 10:43 PM, Stanimir Varbanov wrote: Add a PCIe PHY driver used by PCIe host controller driver on Qualcomm SoCs like Snapdragon 805. Signed-off-by: Stanimir Varbanov

[PATCH 0/3] pinctrl: Qualcomm msm8916 pinctrl driver

for register addresses pinctrl: qcom: Add msm8916 pinctrl driver Stanimir Varbanov (1): DT: pinctrl: Document Qualcomm MSM8916 pinctrl binding .../bindings/pinctrl/qcom,msm8916-pinctrl.txt | 186 +++ drivers/pinctrl/qcom/Kconfig |8 + drivers/pinctrl/qcom

[PATCH 3/3] pinctrl: qcom: Add msm8916 pinctrl driver

From: Joonwoo Park joonw...@codeaurora.org Add initial pinctrl driver to support pin configuration with pinctrl framework for msm8916. Signed-off-by: Joonwoo Park joonw...@codeaurora.org Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com --- drivers/pinctrl/qcom/Kconfig |8

[PATCH 1/3] pinctrl: qcom: increase variable size for register addresses

From: Joonwoo Park joonw...@codeaurora.org Newer MSM SoCs have TLMM hardware block upper than 16 bit. Increase to 32 bit registers to hold addresses correctly. Signed-off-by: Joonwoo Park joonw...@codeaurora.org Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com --- drivers/pinctrl/qcom

[PATCH 2/3] DT: pinctrl: Document Qualcomm MSM8916 pinctrl binding

Adds devicetree binding documentation. Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com --- .../bindings/pinctrl/qcom,msm8916-pinctrl.txt | 186 1 files changed, 186 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom

Re: [PATCH] dmaengine: qcom_bam_dma: add one more optional clock

Hi Andy, On 09/07/2014 08:55 PM, Stanimir Varbanov wrote: The BAM is tightly coupled with the peripheral to which it belongs. In that sprit to access the BAM configuration registers the driver needs to enable some peripheral clocks. Currently the DT node enables bamclk which seems

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