Hi,
On Thu, 2015-07-09 at 08:55 +0530, Sricharan R wrote:
snip
#define ONE_BYTE 0x1
+#define QUP_I2C_MX_CONFIG_DURING_RUN BIT(31)
struct qup_i2c_block {
int count;
@@ -121,6 +122,7 @@ struct qup_i2c_block {
int rx_tag_len;
int
The definition of i2c_msg says that
If this is the last message in a group, it is followed by a STOP.
Otherwise it is followed by the next @i2c_msg transaction segment,
beginning with a (repeated) START
So the expectation is that there is no 'STOP' bit inbetween individual
i2c_msg segments with
