On Fri, Aug 29, 2014 at 4:30 PM, Pramod Gurav
pramod.gu...@smartplayin.com wrote:
This patch adds support for reset functions to reboot the boards
with soc apq8064.
CC: Linus Walleij linus.wall...@linaro.org
CC: Bjorn Andersson bjorn.anders...@sonymobile.com
CC: Ivan T. Ivanov
This set of patches adds pinctrl support for the Qualcomm APQ8084 platform.
The first patch adds the pin definitions. The second patch contains the
devicetree binding documentation. The third patch adds the DT node.
The last patch makes the INTR_TARGET_PROC_APPS value configurable and
defines it
This patchset adds pinctrl support for the Qualcomm APQ8084 platform.
Reviewed-by: Andy Gross agr...@codeaurora.org
Signed-off-by: Georgi Djakov gdja...@mm-sol.com
---
drivers/pinctrl/qcom/Kconfig |8 +
drivers/pinctrl/qcom/Makefile |1 +
Currently the value used for specify that interrupts from the gpio should
be routed to the application processor is hardcoded for all Qualcomm SoCs.
But the new APQ8084 SoC uses a different value. To resolve this, we make
this value configurable for each SoC. For all existing SoCs we continue
to
Add basic support for the IFC6540 single-board computer boards, that are
based on the APQ8084 SoC. The first patch adds the initial device tree.
The second enables the serial console. The third adds the SDHC nodes and
enables the eMMC.
Should go through the qcom/arm-soc tree.
Changes since v1:
Enable support for the two SD host controllers on the APQ8084 platform
by adding the required nodes to the DT files.
On the IFC6540 board, the first controller is connected to the onboard
eMMC and the second is connected to a micro-SD card slot.
Signed-off-by: Georgi Djakov gdja...@mm-sol.com
---
Enable the serial port on the IFC6540 boards.
Signed-off-by: Georgi Djakov gdja...@mm-sol.com
---
arch/arm/boot/dts/qcom-apq8084-ifc6540.dts |6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts
b/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts
index
Add initial device tree for the IFC6540 Snapdragon 805 pico-itx
single-board computer.
Signed-off-by: Georgi Djakov gdja...@mm-sol.com
---
arch/arm/boot/dts/Makefile |1 +
arch/arm/boot/dts/qcom-apq8084-ifc6540.dts |6 ++
2 files changed, 7 insertions(+)
create mode
Hi Grant,
I came down to this. Could you review? Is that
implementation closer to the suggestion made by you.
---
drivers/of/address.c | 49
drivers/of/platform.c | 20 ++---
include/linux/of_address.h | 19
On Sep 2, 2014, at 10:40 AM, Georgi Djakov gdja...@mm-sol.com wrote:
Add basic support for the IFC6540 single-board computer boards, that are
based on the APQ8084 SoC. The first patch adds the initial device tree.
The second enables the serial console. The third adds the SDHC nodes and
On Tue 02 Sep 06:13 PDT 2014, Georgi Djakov wrote:
This patchset adds pinctrl support for the Qualcomm APQ8084 platform.
Reviewed-by: Andy Gross agr...@codeaurora.org
Signed-off-by: Georgi Djakov gdja...@mm-sol.com
I was expecting patch 4 to come before this, so that this commit would be
On Tue 02 Sep 06:13 PDT 2014, Georgi Djakov wrote:
Define a new binding for the Qualcomm TLMM (Top-Level Mode Mux) based pin
controller inside the APQ8084.
Acked-by: Bjorn Andersson bjorn.anders...@sonymobile.com
Don't remember giving you this...
But, with the s/sdc3/sdc2 below I think it
On Tue 02 Sep 06:13 PDT 2014, Georgi Djakov wrote:
Currently the value used for specify that interrupts from the gpio should
be routed to the application processor is hardcoded for all Qualcomm SoCs.
But the new APQ8084 SoC uses a different value. To resolve this, we make
this value
On Tue 02 Sep 05:36 PDT 2014, Linus Walleij wrote:
A bit dirty to have this in this driver, but who cares.
Indeed, but we figured the taint was small enough to justify not creating
cross-references to a separate driver.
Does the APQ8064 accompanying PMIC also have the ability to
completely
On 8/29/2014 5:14 PM, Bjorn Andersson wrote:
From: Kumar Gala ga...@codeaurora.org
Add driver for Qualcomm MSM Hardware Mutex block that exists on
newer Qualcomm SoCs.
Cc: Jeffrey Hugo jh...@codeaurora.org
Cc: Eric Holmberg eholm...@codeaurora.org
Cc: Courtney Cavin
On Tue 02 Sep 10:28 PDT 2014, Jeffrey Hugo wrote:
diff --git a/drivers/hwspinlock/msm_hwspinlock.c
b/drivers/hwspinlock/msm_hwspinlock.c
[..]
+ * Copyright (c) 2013, The Linux Foundation. All rights reserved.
Should the copyright range be updated to include your changes which I
Follow the scm.c and move scm-boot files to drivers/soc/qcom. The
guidance is to clean files out from mach-qcom and move to drivers/soc
area.
Signed-off-by: Lina Iyer lina.i...@linaro.org
---
arch/arm/mach-qcom/Makefile | 1 -
arch/arm/mach-qcom/platsmp.c
From: Kumar Gala ga...@codeaurora.org
Add driver for Qualcomm Hardware Mutex block that exists on newer
Qualcomm SoCs.
Cc: Jeffrey Hugo jh...@codeaurora.org
Cc: Eric Holmberg eholm...@codeaurora.org
Cc: Courtney Cavin courtney.ca...@sonymobile.com
Signed-off-by: Kumar Gala ga...@codeaurora.org
On 09/02/14 14:44, Mike Turquette wrote:
Quoting Stephen Boyd (2014-08-29 12:49:26)
The pre-divider for the sdc clocks only has 2 bits in it, so we
can't possibly divide by anything larger than 4 here.
Furthermore, we program the value of ~(n - m) and the n value is
larger than 8 bits (max of
On 9/2/2014 2:04 PM, Bjorn Andersson wrote:
From: Kumar Gala ga...@codeaurora.org
Add driver for Qualcomm Hardware Mutex block that exists on newer
Qualcomm SoCs.
Cc: Jeffrey Hugo jh...@codeaurora.org
Cc: Eric Holmberg eholm...@codeaurora.org
Cc: Courtney Cavin courtney.ca...@sonymobile.com
If we're tuning on a big-endian CPU we'll never determine we properly
tuned the device because we compare the data we received from the
controller with a table that assumes the CPU is little-endian.
Change the table to be an array of bytes instead of 32-bit words
so we can use memcmp() without
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