On 08/01/2015 03:32 PM, Laurent Pinchart wrote:
Hi Archit,
Thank you for the patch.
On Monday 13 July 2015 12:13:52 Archit Taneja wrote:
Remove FB_* config options since the driver doesn't call any fbdev
functions directly.
Remove FB_KMS_HELPER as this would now be selected by the top
On Tue, 04 Aug, at 08:41:36AM, Zhang, Jonathan Zhixiong wrote:
On 8/3/2015 9:25 PM, Borislav Petkov wrote:
On Mon, Aug 03, 2015 at 05:23:54PM +0100, Matt Fleming wrote:
Rafael, Boris?
The ghes.c change looks fine I guess. The whole patchset makes sense
now, with the arch bits extracted.
On Tue, 04 Aug, at 06:25:52AM, Borislav Petkov wrote:
On Mon, Aug 03, 2015 at 05:23:54PM +0100, Matt Fleming wrote:
Rafael, Boris?
The ghes.c change looks fine I guess. The whole patchset makes sense
now, with the arch bits extracted. So
Acked-by: Borislav Petkov b...@suse.de
Thanks
On Thu, Jul 30, 2015 at 04:17:03PM -0500, Andy Gross wrote:
The following changes since commit d770e558e21961ad6cfdf0ff7df0eb5d7d4f0754:
Linux 4.2-rc1 (2015-07-05 11:01:52 -0700)
are available in the git repository at:
git://codeaurora.org/quic/kernel/agross-msm.git
On Thu, Jul 30, 2015 at 04:16:47PM -0500, Andy Gross wrote:
The following changes since commit d770e558e21961ad6cfdf0ff7df0eb5d7d4f0754:
Linux 4.2-rc1 (2015-07-05 11:01:52 -0700)
are available in the git repository at:
git://codeaurora.org/quic/kernel/agross-msm.git
On Thu, Jul 30, 2015 at 04:16:37PM -0500, Andy Gross wrote:
The following changes since commit d770e558e21961ad6cfdf0ff7df0eb5d7d4f0754:
Linux 4.2-rc1 (2015-07-05 11:01:52 -0700)
are available in the git repository at:
git://codeaurora.org/quic/kernel/agross-msm.git
On 8/5/2015 2:21 AM, Matt Fleming wrote:
On Tue, 04 Aug, at 08:41:36AM, Zhang, Jonathan Zhixiong wrote:
On 8/3/2015 9:25 PM, Borislav Petkov wrote:
On Mon, Aug 03, 2015 at 05:23:54PM +0100, Matt Fleming wrote:
Rafael, Boris?
The ghes.c change looks fine I guess. The whole patchset makes
On Wed, 05 Aug, at 08:58:52AM, Zhang, Jonathan Zhixiong wrote:
Yes, absolutely. It has been in my mind, sorry I was tied up in the last
few days. I wonder what I may missed, I certainly do x86 build test with
versions of the patch set.
I will try today and report back.
No problem.
I'd
Enable PM_CPU_DOMAIN and its PM_GENERIC_DOMAINS dependenciesd to provide
cpu domain support for QCOM SoCs.
Signed-off-by: Lina Iyer lina.i...@linaro.org
---
drivers/soc/qcom/Kconfig | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig
index
The hwspinlock framework, uses a s/w spin lock around the hw spinlock to
ensure that only process acquires the lock at any time. This is the most
general use case. A special case is where a hwspinlock may be acquired
in Linux and a remote entity may release the lock. In such a case, the
s/w
Hwspinlocks are widely used between processors in an SoC, and also
between elevation levels within in the same processor. QCOM SoC's use
hwspinlock to serialize entry into a low power mode when the context
switches from Linux to secure monitor.
Lock #7 has been assigned for this purpose. In
When the last CPU enters idle, the state of L2 is determined and the
power controller for the L2 is programmed to power down. The power
controllers' state machine is only triggered when all the CPUs have
executed their WFI instruction. Multiple CPUs may enter SCM to power
down at the same time.
Add device binding for hwspinlock support on QCOM 8084 SoCs.
Signed-off-by: Lina Iyer lina.i...@linaro.org
---
arch/arm/boot/dts/qcom-apq8084.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi
b/arch/arm/boot/dts/qcom-apq8084.dtsi
index
On APQ8084 QCOM SoC's, the CPUs are powered by a single rail controlled
by the L2 cache power controller (L2 SPM). The L2 power domain supplies
power to all the CPUs and L2. It is safe to power down the domain when
all the CPUs and the L2 are powered down.
Powering down of the domain is done
Recognize cache SPM devices defined in the DT and configure the
corresponding SPM hardware. SPM controllers for L2 controls the cache's
idle low power state and may also be used to turn off the CPU power
rail.
Cc: Stephen Boyd sb...@codeaurora.org
Cc: Andy Gross agr...@codeaurora.org
Add register data and configure L2 SAW to support voltage control and L2
idle states for QCOM APQ8084 SoC.
Signed-off-by: Lina Iyer lina.i...@linaro.org
---
.../devicetree/bindings/arm/msm/qcom,saw2.txt | 1 +
drivers/soc/qcom/spm.c| 19
Add power controller (SAW) device nodes for L2 caches. L2 SAW enable L2
to enter idle states and be powered off. Also, on 8084 the L2 SAW may be
used to regulate the active voltage for the cpu and L2.
Signed-off-by: Lina Iyer lina.i...@linaro.org
---
arch/arm/boot/dts/qcom-apq8084.dtsi | 4 ++--
Define L2 SAW as the power domain provider and individual cpus are the
power domain consumers.
Signed-off-by: Lina Iyer lina.i...@linaro.org
---
arch/arm/boot/dts/qcom-apq8084.dtsi | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi
This patchset add support to power down the L2 and the PM domain for the CPU
subsystem on Qualcomm's APQ8084. Only 8084 is supported at this time, because
the firmware for chipsets prior to 8084 (8074, 8064) will allow the domain to
be powered off only when running as a single core system. That
On Wed, Aug 05, 2015 at 10:32:42AM -0600, Lina Iyer wrote:
Enable PM_CPU_DOMAIN and its PM_GENERIC_DOMAINS dependenciesd to provide
cpu domain support for QCOM SoCs.
Fix dependencies sic
Signed-off-by: Lina Iyer lina.i...@linaro.org
---
drivers/soc/qcom/Kconfig | 4
1 file changed,
Pending interrupt status needs to be cleared before enable the
interrupt. Otherwise it's possible to get a pending interrupt instead
of an incoming interrupt.
Signed-off-by: Jilai Wang jil...@codeaurora.org
---
drivers/gpu/drm/msm/mdp/mdp4/mdp4_irq.c | 10 +++---
On 07/28/2015 05:54 AM, Srinivas Kandagatla wrote:
@@ -618,5 +633,77 @@
compatible = qcom,tcsr-apq8064, syscon;
reg = 0x1a40 0x100;
};
+
+ hdmi: qcom,hdmi-tx@4a0 {
+ compatible =
On 04/28/2015 12:23 PM, Kumar Gala wrote:
+
+int __qcom_scm_call_armv8_64(u64 x0, u64 x1, u64 x2, u64 x3, u64 x4, u64 x5,
+ u64 *ret1, u64 *ret2, u64 *ret3)
+{
+ register u64 r0 asm(r0) = x0;
+ register u64 r1 asm(r1) = x1;
+ register u64 r2
On Wed, Aug 05, 2015 at 06:27:24PM -0700, Stephen Boyd wrote:
On 04/28/2015 12:23 PM, Kumar Gala wrote:
+
+int __qcom_scm_call_armv8_64(u64 x0, u64 x1, u64 x2, u64 x3, u64 x4, u64 x5,
+u64 *ret1, u64 *ret2, u64 *ret3)
+{
+register u64 r0 asm(r0) = x0;
+
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