On Thu, Jan 09, 2014 at 08:52:21PM +, Stephen Boyd wrote:
On 01/08/14 02:05, Lorenzo Pieralisi wrote:
On Tue, Jan 07, 2014 at 08:12:39PM +, Stephen Boyd wrote:
On 01/07, Lorenzo Pieralisi wrote:
I have a problem with the cache level definition, and in
particular the numbering,
On Thu, Jan 09, 2014 at 07:17:29PM +, Stephen Boyd wrote:
On 01/09/14 02:49, Will Deacon wrote:
+static irq_handler_t cpu_handler;
+
+static irqreturn_t cpu_pmu_dispatch_irq(int irq, void *dev)
+{
+ struct arm_pmu *arm_pmu = *(struct arm_pmu **)dev;
+ return cpu_handler(irq,
On Thu, Jan 09, 2014 at 07:57:12PM +, Stephen Boyd wrote:
(Adding DT reviewers)
On 01/09/14 03:04, Will Deacon wrote:
On Wed, Jan 08, 2014 at 10:59:40PM +, Stephen Boyd wrote:
+static int krait_pmu_init(struct arm_pmu *cpu_pmu)
+{
+ u32 id = read_cpuid_id() 0xff00;
+
On 01/10, Will Deacon wrote:
On Thu, Jan 09, 2014 at 07:57:12PM +, Stephen Boyd wrote:
(Adding DT reviewers)
On 01/09/14 03:04, Will Deacon wrote:
On Wed, Jan 08, 2014 at 10:59:40PM +, Stephen Boyd wrote:
+static int krait_pmu_init(struct arm_pmu *cpu_pmu)
+{
+
This patch set introduces the dmaengine driver for the Qualcomm Bus Access
Manager (BAM) DMA controller present on MSM 8x74 devices. A number of the
on-chip devices have their own BAM DMA controller and use it to move data
between system memory and peripherals or between two peripherals.
The
Add device tree binding support for the QCOM BAM DMA driver.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
.../devicetree/bindings/dma/qcom_bam_dma.txt | 52 ++
1 file changed, 52 insertions(+)
create mode 100644
Add the DMA engine driver for the QCOM Bus Access Manager (BAM) DMA controller
found in the MSM 8x74 platforms.
Each BAM DMA device is associated with a specific on-chip peripheral. Each
channel provides a uni-directional data transfer engine that is capable of
transferring data between the
ARCH_MSM is a hidden config option now so this defconfig needs to
be updated to select ARCH_MSM_DT instead. While we're here,
remove dead symbols (SSBI), drop selected symbols (ZRELADDR,
PHYLIB, USB_PHY) and enable the MSM random driver (HW_RANDOM_MSM).
Cc: Kevin Hilman
On 01/10, Will Deacon wrote:
On Thu, Jan 09, 2014 at 07:17:29PM +, Stephen Boyd wrote:
We can avoid the hacky cast of the per-cpu dev token by using the
cpu_pmu pointer directly, but we'll still need to pass something to the
percpu interrupt handler otherwise the genirq layer doesn't
