On 24 February 2014 13:12, Srivatsa S. Bhat
srivatsa.b...@linux.vnet.ibm.com wrote:
On 02/24/2014 12:27 PM, Saravana Kannan wrote:
The existing code sets the per CPU policy to a non-NULL value before all
the steps performed during the hotplug online path is done. Specifically,
this is done
+CI13xxx (Chipidea) USB controllers
+
+Required properties:
+- compatible: should contain qcom,ci-hdrc
+- reg: offset and length of the register set in the memory map
+- interrupts: interrupt-specifier for the controller interrupt.
+- usb-phy: phandle for the PHY device
Srivatsa S. Bhat wrote:
On 02/24/2014 12:27 PM, Saravana Kannan wrote:
The existing code sets the per CPU policy to a non-NULL value before all
the steps performed during the hotplug online path is done.
Specifically,
this is done before the policy min/max, governors, etc are initialized
Viresh Kumar wrote:
On 24 February 2014 13:12, Srivatsa S. Bhat
srivatsa.b...@linux.vnet.ibm.com wrote:
On 02/24/2014 12:27 PM, Saravana Kannan wrote:
The existing code sets the per CPU policy to a non-NULL value before
all
the steps performed during the hotplug online path is done.
On 24 February 2014 14:11, skan...@codeaurora.org wrote:
I just replied to the other email. I think I answered both your questions
there. Sorry about mixing up CPU and policy. In my case, each CPU is
independently scalable -- so for now take CPU == policy. I'll fix it up
once we agree on the
Viresh Kumar wrote:
On 24 February 2014 14:11, skan...@codeaurora.org wrote:
I just replied to the other email. I think I answered both your
questions
there. Sorry about mixing up CPU and policy. In my case, each CPU is
independently scalable -- so for now take CPU == policy. I'll fix it up
On 24 February 2014 14:17, skan...@codeaurora.org wrote:
Sorry, not sure I understand what you mean.
I agree, wording in my commit text might be unclear. I'll fix it after we
agree on the code fix. In the MSM case, each CPU has it's own policy.
I'm assuming your original complaint was about
Viresh Kumar wrote:
On 24 February 2014 14:17, skan...@codeaurora.org wrote:
Sorry, not sure I understand what you mean.
I agree, wording in my commit text might be unclear. I'll fix it after
we
agree on the code fix. In the MSM case, each CPU has it's own policy.
I'm assuming your
On Thu, Feb 6, 2014 at 4:28 PM, Ivan T. Ivanov iiva...@mm-sol.com wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
Add pin, group and function definitions for SPI#8
controller.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
Patch applied with Björn's ACK.
Thanks!
Linus Walleij
--
To
On Thu, Feb 6, 2014 at 4:28 PM, Ivan T. Ivanov iiva...@mm-sol.com wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
Add the pin control node and pin definitions of SPI8.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
Acked-by: Linus Walleij linus.wall...@linaro.org
Kumar, please take this
On Mon, 2014-02-24 at 08:15 +, Peter Chen wrote:
+CI13xxx (Chipidea) USB controllers
+
+Required properties:
+- compatible: should contain qcom,ci-hdrc
+- reg: offset and length of the register set in the memory map
+- interrupts: interrupt-specifier for the
Hi,
On Wed, 2014-02-19 at 09:46 -0800, Courtney Cavin wrote:
On Wed, Feb 19, 2014 at 04:43:22PM +0100, Ivan T. Ivanov wrote:
Hi,
On Tue, 2014-02-18 at 13:26 -0800, Courtney Cavin wrote:
On Tue, Feb 18, 2014 at 02:21:19PM +0100, Ivan T. Ivanov wrote:
From: Ivan T. Ivanov
Hi,
On Fri, 2014-02-21 at 09:35 -0600, Kumar Gala wrote:
On Feb 20, 2014, at 6:38 PM, Bjorn Andersson bjorn.anders...@sonymobile.com
wrote:
This bus driver supports the QUP i2c hardware controller in the Qualcomm
SOCs.
The Qualcomm Universal Peripheral Engine (QUP) is a general
On Mon, 2014-02-24 at 08:15 +, Peter Chen wrote:
+CI13xxx (Chipidea) USB controllers
+
+Required properties:
+- compatible: should contain qcom,ci-hdrc
+- reg: offset and length of the register set in the memory
map
+- interrupts: interrupt-specifier for
On 24 February 2014 14:09, skan...@codeaurora.org wrote:
Srivatsa S. Bhat wrote:
On 02/24/2014 12:27 PM, Saravana Kannan wrote:
The existing code sets the per CPU policy to a non-NULL value before all
the steps performed during the hotplug online path is done.
Specifically,
this is done
Automated build testing of allmodconfig discovered this error in the
MSM DRM driver:
drivers/gpu/drm/msm/hdmi/hdmi.o:(.rodata+0x10): multiple definition of
`__mod_of_device_table'
drivers/gpu/drm/msm/adreno/a3xx_gpu.o:(.rodata+0x4dc): first defined here
It appears that this will happen whenever
On Mon, Feb 24, 2014 at 6:15 AM, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
Automated build testing of allmodconfig discovered this error in the
MSM DRM driver:
drivers/gpu/drm/msm/hdmi/hdmi.o:(.rodata+0x10): multiple definition of
`__mod_of_device_table'
On Mon, Feb 24, 2014 at 12:33:10PM +0200, Ivan T. Ivanov wrote:
On Fri, 2014-02-21 at 09:35 -0600, Kumar Gala wrote:
On Feb 20, 2014, at 6:38 PM, Bjorn Andersson
bjorn.anders...@sonymobile.com wrote:
This bus driver supports the QUP i2c hardware controller in the Qualcomm
SOCs.
On Thu 20 Feb 18:53 PST 2014, Emilio L?pez wrote:
Hi Bjorn,
El 20/02/14 21:38, Bjorn Andersson escribió:
[...]
+ clk_freq = 10;
+ if (!of_property_read_u32(node, clock-frequency, val))
+ clk_freq = val;
val will be modified only if no error occurs, so you may
On Fri 21 Feb 00:16 PST 2014, Maxime Ripard wrote:
Hi Bjorn,
On Thu, Feb 20, 2014 at 04:38:10PM -0800, Bjorn Andersson wrote:
+static int qup_i2c_probe(struct platform_device *pdev)
+{
[ snip ]
+
+ qup_i2c_enable_clocks(qup);
+
[ snip ]
+
+
On Mon 24 Feb 09:40 PST 2014, Josh Cartwright wrote:
On Mon, Feb 24, 2014 at 12:33:10PM +0200, Ivan T. Ivanov wrote:
On Fri, 2014-02-21 at 09:35 -0600, Kumar Gala wrote:
On Feb 20, 2014, at 6:38 PM, Bjorn Andersson
bjorn.anders...@sonymobile.com wrote:
This bus driver supports
On Mon, Feb 24, 2014 at 10:14:45AM -0800, Randy Dunlap wrote:
On 02/24/2014 09:46 AM, Bjorn Andersson wrote:
On Mon 24 Feb 06:46 PST 2014, Linus Walleij wrote:
On Mon, Feb 17, 2014 at 6:33 PM, Randy Dunlap rdun...@infradead.org
wrote:
On 02/16/2014 10:23 PM, Stephen Rothwell wrote:
On 02/24/2014 10:41 AM, Josh Cartwright wrote:
On Mon, Feb 24, 2014 at 10:14:45AM -0800, Randy Dunlap wrote:
On 02/24/2014 09:46 AM, Bjorn Andersson wrote:
On Mon 24 Feb 06:46 PST 2014, Linus Walleij wrote:
On Mon, Feb 17, 2014 at 6:33 PM, Randy Dunlap rdun...@infradead.org
wrote:
On
On Mon 24 Feb 10:41 PST 2014, Josh Cartwright wrote:
[...]
Without too much effort, I can get this to fail just by making
CONFIG_PINCTRL_MSM=m. handle_bad_irq isn't marked EXPORT_SYMBOL*, so
hence the warning.
Ohh, yeah I missed that.
Whether or not this is intentional is not clear.
On 02/24/2014 02:55 AM, Viresh Kumar wrote:
On 24 February 2014 14:09, skan...@codeaurora.org wrote:
Srivatsa S. Bhat wrote:
On 02/24/2014 12:27 PM, Saravana Kannan wrote:
The existing code sets the per CPU policy to a non-NULL value before all
the steps performed during the hotplug online
Add the DMA engine driver for the QCOM Bus Access Manager (BAM) DMA controller
found in the MSM 8x74 platforms.
Each BAM DMA device is associated with a specific on-chip peripheral. Each
channel provides a uni-directional data transfer engine that is capable of
transferring data between the
Add device tree binding support for the QCOM BAM DMA driver.
Acked-by: Kumar Gala ga...@codeaurora.org
Signed-off-by: Andy Gross agr...@codeaurora.org
---
.../devicetree/bindings/dma/qcom_bam_dma.txt | 41
1 file changed, 41 insertions(+)
create mode 100644
Hi,
On Mon, Feb 24, 2014 at 05:11:40PM -0600, Andy Gross wrote:
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 605b016..f87cef9 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -401,4 +401,13 @@ config DMATEST
config DMA_ENGINE_RAID
bool
+config
Hi,
On Wed, 2014-02-19 at 09:46 -0800, Courtney Cavin wrote:
On Wed, Feb 19, 2014 at 04:43:22PM +0100, Ivan T. Ivanov wrote:
Hi,
On Tue, 2014-02-18 at 13:26 -0800, Courtney Cavin wrote:
On Tue, Feb 18, 2014 at 02:21:19PM +0100, Ivan T. Ivanov wrote:
From: Ivan T.
On Mon, Feb 24, 2014 at 06:09:13PM -0600, Felipe Balbi wrote:
+ depends on ARCH_QCOM || (COMPILE_TEST OF ARM)
do you really want to make it depend on ARM even when COMPILE_TEST=y ?
writel_relaxed() is unfortunately not generally available so it'd fail
to build on platforms like x86.
On 12/24/2013 3:00 PM, Manu Gautam wrote:
Allow userspace to pass SuperSpeed descriptors and
handle them in the driver accordingly.
This change doesn't modify existing desc_header and thereby
keeps the ABI changes backward compatible i.e. existing
userspace drivers compiled with old header
On Tue, Feb 25, 2014 at 12:05:00PM +0900, Mark Brown wrote:
On Mon, Feb 24, 2014 at 06:09:13PM -0600, Felipe Balbi wrote:
+ depends on ARCH_QCOM || (COMPILE_TEST OF ARM)
do you really want to make it depend on ARM even when COMPILE_TEST=y ?
writel_relaxed() is unfortunately not
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