Some gdsc instances require a certain root clock (RCG) to be turned on
*before* the power domain itself can be turned on. Handle this as part
of the gdsc enable/disable callbacks.
Signed-off-by: Rajendra Nayak rna...@codeaurora.org
---
drivers/clk/qcom/gcc-msm8916.c | 1 +
The devices within a gdsc power domain, quite often have additional
clocks to be turned on/off along with the power domain itself.
Once the drivers for these devices are converted to use runtime PM,
it would be possible to remove all clock handling from the drivers if
the gdsc driver can handle
msm8974 has gcc and mmcc nodes, and apq8084 has a gcc node which
implement gdsc powerdomains. Add the #power-domain-cells property
to them.
Signed-off-by: Rajendra Nayak rna...@codeaurora.org
---
arch/arm/boot/dts/qcom-apq8084.dtsi | 1 +
arch/arm/boot/dts/qcom-msm8974.dtsi | 2 ++
Along with the GDSC power switch, there is additional control
to either retain all memory (core and peripheral) within a given
powerdomain or to turn them off while the GDSC is powered down.
Add support for these by modelling a RET state where all
memory is retained and an OFF state where all
From: Stephane Viau sv...@codeaurora.org
Add the GDSC instances that exist as part of apq8084 MMCC block.
Signed-off-by: Stephane Viau sv...@codeaurora.org
Signed-off-by: Rajendra Nayak rna...@codeaurora.org
---
drivers/clk/qcom/Kconfig | 1 +
On 07/31/2015 08:24 PM, Stanimir Varbanov wrote:
snip
+static struct gdsc venus0_gdsc = {
+ .gdscr = 0x1024,
+ .pd = {
+ .name = venus0,
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .con_ids = { NULL },
+};
+
Rajendra, according to downstream kernel
From: Stephen Boyd sb...@codeaurora.org
GDSCs (Global Distributed Switch Controllers) are responsible for
safely collapsing and restoring power to peripherals in the SoC.
These are best modelled as power domains using genpd and given
the registers are scattered throughout the clock controller
GDSCs (Global Distributed Switch Controllers) control switches
that supply power to an on-chip power domain and hence can be
programmed in SW to safely power collapse and restore power to the
respective PDs. They are part of a considerable number of recent QCOM
SoCs (This series adds support for
The common clk probe registers a clk provider and a reset controller.
Update it to register a genpd provider using the gdsc data provided
by each platform.
Signed-off-by: Rajendra Nayak rna...@codeaurora.org
---
drivers/clk/qcom/common.c | 15 ++-
drivers/clk/qcom/common.h | 2 ++
2
Add all data for the GDSCs which are part of msm8916 GCC block.
Signed-off-by: Rajendra Nayak rna...@codeaurora.org
---
drivers/clk/qcom/Kconfig | 1 +
drivers/clk/qcom/gcc-msm8916.c | 51
Certain devices can have GDSCs' which support ON as the only state.
They can't be power collapsed to either hit RET or OFF.
The clients drivers for these GDSCs' however would expect the state
of the core to be reset following a GDSC disable and re-enable.
To do this assert/deassert reset lines
On Wed, Aug 5, 2015 at 9:27 PM, Stephen Boyd sb...@codeaurora.org wrote:
On 07/28/2015 05:54 AM, Srinivas Kandagatla wrote:
@@ -618,5 +633,77 @@
compatible = qcom,tcsr-apq8064, syscon;
reg = 0x1a40 0x100;
};
+
+
On Thu, Aug 06, 2015 at 06:19:58PM +0100, Mark Brown wrote:
On Thu, Aug 06, 2015 at 12:00:47PM +0100, Build bot for Mark Brown wrote:
Today's linux-next fails to build an arm64 allmodconfig due to:
arm64-allmodconfig
ERROR: qcom_scm_hdcp_req [drivers/gpu/drm/msm/msm.ko] undefined!
On Thu, Aug 06, 2015 at 12:00:47PM +0100, Build bot for Mark Brown wrote:
Today's linux-next fails to build an arm64 allmodconfig due to:
arm64-allmodconfig
ERROR: qcom_scm_hdcp_req [drivers/gpu/drm/msm/msm.ko] undefined!
ERROR: qcom_scm_hdcp_available [drivers/gpu/drm/msm/msm.ko]
Hello Rob,
On 8/3/2015 10:13 AM, Rob Herring wrote:
On Mon, Aug 3, 2015 at 1:59 AM, Sagar Dharia sdha...@codeaurora.org wrote:
OF helper routine scans the SLIMbus DeviceTree, allocates resources,
and creates slim_devices according to the hierarchy.
Signed-off-by: Sagar Dharia
On 8/5/2015 9:13 AM, Matt Fleming wrote:
On Wed, 05 Aug, at 05:10:00PM, Matt Fleming wrote:
On Wed, 05 Aug, at 08:58:52AM, Zhang, Jonathan Zhixiong wrote:
Yes, absolutely. It has been in my mind, sorry I was tied up in the last
few days. I wonder what I may missed, I certainly do x86 build
From: Jonathan (Zhixiong) Zhang zjzh...@codeaurora.org
On a platform with APEI (ACPI Platform Error Interface) enabled, firmware
updates a memory region with hardware error record using nocache
attribute. When OS reads the region, since it maps the region with
cacahed attribute even though EFI
On Wednesday, July 22, 2015 9:45 AM, Bjorn Andersson wrote:
The Qualcomm PM8941 WLED block is used for backlight and should therefor
be in the backlight framework and not in the LED framework. This moves
the driver and adapts to the backlight api instead.
Acked-by: Jacek Anaszewski
18 matches
Mail list logo
