[PATCH] pinctrl: fix qcom ssbi drivers for 64-bit compilation

[Arnd Bergmann]

When building pinctrl-ssbi-gpio and pinctrl-ssbi-mpp for ARM64, we get
a compile warning about invalid types:

drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c: In function 'pm8xxx_gpio_probe':
drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c:675:17: warning: cast from pointer to 
integer of different size [-Wpointer-to-int-cast]
drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c: In function 'pm8xxx_mpp_probe':
drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c:766:17: warning: cast from pointer to 
integer of different size [-Wpointer-to-int-cast]

This changes the code so we cast the pointer to 'unsigned long', which
is the right thing to do here.

Signed-off-by: Arnd Bergmann 

diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c 
b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c
index d809c9eaa323..19a3c3bc2f1f 100644
--- a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c
+++ b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c
@@ -672,7 +672,7 @@ static int pm8xxx_gpio_probe(struct platform_device *pdev)
return -ENOMEM;
 
pctrl->dev = >dev;
-   pctrl->npins = (unsigned)of_device_get_match_data(>dev);
+   pctrl->npins = (unsigned long)of_device_get_match_data(>dev);
 
pctrl->regmap = dev_get_regmap(pdev->dev.parent, NULL);
if (!pctrl->regmap) {
diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c 
b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c
index 8982027de8e8..b868ef1766a0 100644
--- a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c
+++ b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c
@@ -763,7 +763,7 @@ static int pm8xxx_mpp_probe(struct platform_device *pdev)
return -ENOMEM;
 
pctrl->dev = >dev;
-   pctrl->npins = (unsigned)of_device_get_match_data(>dev);
+   pctrl->npins = (unsigned long)of_device_get_match_data(>dev);
 
pctrl->regmap = dev_get_regmap(pdev->dev.parent, NULL);
if (!pctrl->regmap) {

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Re: [PATCH V5 2/3] dma: add Qualcomm Technologies HIDMA management driver

[Sinan Kaya]

On 11/16/2015 10:58 AM, Arnd Bergmann wrote:
>> The management driver is executed in hypervisor context and
>> > is the main management entity for all channels provided by
>> > the device.
> Sorry for asking this question so late, but can you explain what the
> point is behind this? It seems counterintuitive to me to have a
> DMA engine that is meant for speeding up memory-to-memory transfers
> when you run it in a virtual machine where you either need to go
> through a virtual IOMMU to set up page table entries, as that will
> likely cause more performance overhead than you could possibly
> gain, or you assume that all the guest memory is pinned, which
> in turn destroys a lot of the assumptions that we are making
> in KVM to have useful VM guests.
> 
> Where am I going wrong here?
> 

The behavior of HIDMA is not any different from PCIe. We are using
platform device pass through and giving the control of the entire HIDMA
device to the guest machine. Therefore, we don’t need to trap into host
machine for driver execution.

I agree with the fact that the pages need to be pinned for this to work.
Again, this is not any different from PCIe SRIOV passthrough.

Pinning guest removes use cases like ballooning/overcommit but that is a
choice for end user to make: whether he wants additional I/O performance
or wants higher memory utilization at the cost of lower I/O performance.

-- 
Sinan Kaya
Qualcomm Technologies, Inc. on behalf of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a
Linux Foundation Collaborative Project
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Re: [PATCH V5 2/3] dma: add Qualcomm Technologies HIDMA management driver

[Arnd Bergmann]

On Sunday 15 November 2015 15:54:13 Sinan Kaya wrote:
> The Qualcomm Technologies HIDMA device has been designed
> to support virtualization technology. The driver has been
> divided into two to follow the hardware design.
> 
> 1. HIDMA Management driver
> 2. HIDMA Channel driver
> 
> Each HIDMA HW consists of multiple channels. These channels
> share some set of common parameters. These parameters are
> initialized by the management driver during power up.
> Same management driver is used for monitoring the execution
> of the channels. Management driver can change the performance
> behavior dynamically such as bandwidth allocation and
> prioritization.
> 
> The management driver is executed in hypervisor context and
> is the main management entity for all channels provided by
> the device.

Sorry for asking this question so late, but can you explain what the
point is behind this? It seems counterintuitive to me to have a
DMA engine that is meant for speeding up memory-to-memory transfers
when you run it in a virtual machine where you either need to go
through a virtual IOMMU to set up page table entries, as that will
likely cause more performance overhead than you could possibly
gain, or you assume that all the guest memory is pinned, which
in turn destroys a lot of the assumptions that we are making
in KVM to have useful VM guests.

Where am I going wrong here?

>  .../devicetree/bindings/dma/qcom_hidma_mgmt.txt|  61 
>  drivers/dma/qcom/Kconfig   |  10 +
>  drivers/dma/qcom/Makefile  |   1 +
>  drivers/dma/qcom/hidma_mgmt.c  | 306 
> +
>  drivers/dma/qcom/hidma_mgmt.h  |  38 +++
>  drivers/dma/qcom/hidma_mgmt_sys.c  | 231 

Each sysfs file API you add needs a documentation in Documentation/ABI/.

Arnd
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Re: [PATCH] mfd: ssbi: removing unnecessary strcmp

[Lee Jones]

On Sun, 15 Nov 2015, Saurabh Sengar wrote:

> passing the actual enum value for controller type from device tree,
> instead of passing the string and converting it to enum

Initially I would have probably preferred this version, but I can't
think of a good enough reason to break the current ABI in order to
replace it.

> Signed-off-by: Saurabh Sengar 
> ---
>  Documentation/devicetree/bindings/arm/msm/ssbi.txt |  6 +++---
>  arch/arm/boot/dts/qcom-apq8064.dtsi|  3 ++-
>  arch/arm/boot/dts/qcom-ipq8064.dtsi|  3 ++-
>  arch/arm/boot/dts/qcom-msm8660.dtsi|  3 ++-
>  arch/arm/boot/dts/qcom-msm8960.dtsi|  3 ++-
>  drivers/mfd/ssbi.c | 17 ++---
>  include/dt-bindings/mfd/qcom,ssbi.h| 19 +++
>  7 files changed, 36 insertions(+), 18 deletions(-)
>  create mode 100644 include/dt-bindings/mfd/qcom,ssbi.h
> 
> diff --git a/Documentation/devicetree/bindings/arm/msm/ssbi.txt 
> b/Documentation/devicetree/bindings/arm/msm/ssbi.txt
> index 54fd5ce..61a37e0 100644
> --- a/Documentation/devicetree/bindings/arm/msm/ssbi.txt
> +++ b/Documentation/devicetree/bindings/arm/msm/ssbi.txt
> @@ -10,9 +10,9 @@ These require the following properties:
>  
>  - qcom,controller-type
>indicates the SSBI bus variant the controller should use to talk
> -  with the slave device.  This should be one of "ssbi", "ssbi2", or
> -  "pmic-arbiter".  The type chosen is determined by the attached
> -  slave.
> +  with the slave device.  This should be one of MSM_SBI_CTRL_SSBI,
> +  MSM_SBI_CTRL_SSBI2 or MSM_SBI_CTRL_PMIC_ARBITER.
> +  The type chosen is determined by the attached slave.
>  
>  The slave device should be the single child node of the ssbi device
>  with a compatible field.
> diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi 
> b/arch/arm/boot/dts/qcom-apq8064.dtsi
> index a4c1762..e391a01 100644
> --- a/arch/arm/boot/dts/qcom-apq8064.dtsi
> +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
> @@ -5,6 +5,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  / {
>   model = "Qualcomm APQ8064";
> @@ -339,7 +340,7 @@
>   qcom,ssbi@50 {
>   compatible = "qcom,ssbi";
>   reg = <0x0050 0x1000>;
> - qcom,controller-type = "pmic-arbiter";
> + qcom,controller-type = ;
>  
>   pmicintc: pmic@0 {
>   compatible = "qcom,pm8921";
> diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi 
> b/arch/arm/boot/dts/qcom-ipq8064.dtsi
> index fa69863..a3ba13a 100644
> --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
> +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
> @@ -3,6 +3,7 @@
>  #include "skeleton.dtsi"
>  #include 
>  #include 
> +#include 
>  #include 
>  
>  / {
> @@ -307,7 +308,7 @@
>   qcom,ssbi@50 {
>   compatible = "qcom,ssbi";
>   reg = <0x0050 0x1000>;
> - qcom,controller-type = "pmic-arbiter";
> + qcom,controller-type = ;
>   };
>  
>   gcc: clock-controller@90 {
> diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi 
> b/arch/arm/boot/dts/qcom-msm8660.dtsi
> index e5f7f33..51b28d2 100644
> --- a/arch/arm/boot/dts/qcom-msm8660.dtsi
> +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi
> @@ -4,6 +4,7 @@
>  
>  #include 
>  #include 
> +#include 
>  #include 
>  
>  / {
> @@ -112,7 +113,7 @@
>   qcom,ssbi@50 {
>   compatible = "qcom,ssbi";
>   reg = <0x50 0x1000>;
> - qcom,controller-type = "pmic-arbiter";
> + qcom,controller-type = ;
>  
>   pmicintc: pmic@0 {
>   compatible = "qcom,pm8058";
> diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi 
> b/arch/arm/boot/dts/qcom-msm8960.dtsi
> index 134cd91..d01cee5 100644
> --- a/arch/arm/boot/dts/qcom-msm8960.dtsi
> +++ b/arch/arm/boot/dts/qcom-msm8960.dtsi
> @@ -5,6 +5,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  
>  / {
> @@ -171,7 +172,7 @@
>   qcom,ssbi@50 {
>   compatible = "qcom,ssbi";
>   reg = <0x50 0x1000>;
> - qcom,controller-type = "pmic-arbiter";
> + qcom,controller-type = ;
>  
>   pmicintc: pmic@0 {
>   compatible = "qcom,pm8921";
> diff --git a/drivers/mfd/ssbi.c b/drivers/mfd/ssbi.c
> index 27986f6..cf4d983 100644
> --- a/drivers/mfd/ssbi.c
> +++ b/drivers/mfd/ssbi.c
> @@ -274,7 +274,7 @@ static int ssbi_probe(struct platform_device *pdev)
>   struct device_node *np = pdev->dev.of_node;
>   struct resource *mem_res;
>   struct ssbi *ssbi;
> - const char *type;
> + u32 type;
>  
>   ssbi = devm_kzalloc(>dev, sizeof(*ssbi), 

Re: [PATCH] pinctrl: fix qcom ssbi drivers for 64-bit compilation

[Bjorn Andersson]

On Mon 16 Nov 08:41 PST 2015, Arnd Bergmann wrote:

> When building pinctrl-ssbi-gpio and pinctrl-ssbi-mpp for ARM64, we get
> a compile warning about invalid types:
> 
> drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c: In function 'pm8xxx_gpio_probe':
> drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c:675:17: warning: cast from pointer 
> to integer of different size [-Wpointer-to-int-cast]
> drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c: In function 'pm8xxx_mpp_probe':
> drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c:766:17: warning: cast from pointer to 
> integer of different size [-Wpointer-to-int-cast]
> 
> This changes the code so we cast the pointer to 'unsigned long', which
> is the right thing to do here.
> 
> Signed-off-by: Arnd Bergmann 
> 

Thanks Arnd,

Reviewed-by: Bjorn Andersson 

Regards,
Bjorn
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Re: [PATCH 2/2] usb: phy: msm: fix connect/disconnect bug for dragonboard OTG port

[Felipe Balbi]

Hi,

Peter Chen  writes:
> On Wed, Nov 11, 2015 at 09:48:00AM -0800, Tim Bird wrote:
>> 
>> 
>> On 11/10/2015 07:14 PM, Peter Chen wrote:
>> > On Tue, Nov 10, 2015 at 04:46:51PM -0800, Tim Bird wrote:
>> >> This fixes a bug where if you disconnect and re-connect the USB cable,
>> >> the gadget driver stops working.
>> >>
>> >> Add support for async_irq to wake up driver from low power mode.
>> >> Without this, the power management code never calls resume.
>> >> Also, have the phy driver kick the gadget driver (chipidea otg)
>> >> by having the chipidea driver register with it, for vbus connect
>> >> notifications.
>> >>
>> >> Signed-off-by: Tim Bird 
>> >> ---
>> >>  drivers/usb/chipidea/udc.c|  6 ++
>> >>  drivers/usb/phy/phy-msm-usb.c | 16 
>> >>  include/linux/usb/msm_hsusb.h |  1 +
>> >>  3 files changed, 23 insertions(+)

I just wanna know how you guys want this to be handled ? Through my tree
or chipidea's ? Or do we break the dependencies between the changes ?

-- 
balbi


signature.asc
Description: PGP signature

[PATCH v2 3/5] ARM: qcom: add IPQ4019 compatible match

[Matthew McClintock]

From: Matthew McClintock 

This will select qcom board type when the machine compatible is
qcom,ipq4019.

Signed-off-by: Matthew McClintock 
---
 arch/arm/mach-qcom/board.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-qcom/board.c b/arch/arm/mach-qcom/board.c
index 6d8bbf7..b52a6bc 100644
--- a/arch/arm/mach-qcom/board.c
+++ b/arch/arm/mach-qcom/board.c
@@ -18,6 +18,7 @@ static const char * const qcom_dt_match[] __initconst = {
"qcom,apq8064",
"qcom,apq8074-dragonboard",
"qcom,apq8084",
+   "qcom,ipq4019",
"qcom,ipq8062",
"qcom,ipq8064",
"qcom,msm8660-surf",
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

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[PATCH] Revert "thermal: qcom_spmi: allow compile test"

[Arnd Bergmann]

This just caused build errors:

warning: (QCOM_SPMI_TEMP_ALARM) selects REGMAP_SPMI which has unmet direct 
dependencies (SPMI)
drivers/built-in.o: In function `regmap_spmi_ext_gather_write':
:(.text+0x609b0): undefined reference to `spmi_ext_register_write'
:(.text+0x609f0): undefined reference to `spmi_ext_register_writel'

While it's generally a good idea to allow compile testing, in this
case, it just doesn't work, so reverting the patch that
introduced the compile-test variant seems the most appropriate
solution.

Note that SPIMI also has a 'depends on ARCH_QCOM || COMPILE_TEST'
statement, so we should be able to enable SPMI on all architectures
for compile testing already.

Signed-off-by: Arnd Bergmann 
Fixes: cb7fb4d34202 ("thermal: qcom_spmi: allow compile test")

diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
index 2e7524f0f3f7..6045b17d0e00 100644
--- a/drivers/thermal/Kconfig
+++ b/drivers/thermal/Kconfig
@@ -381,7 +381,7 @@ endmenu
 
 config QCOM_SPMI_TEMP_ALARM
tristate "Qualcomm SPMI PMIC Temperature Alarm"
-   depends on OF && (SPMI || COMPILE_TEST) && IIO
+   depends on OF && SPMI && IIO
select REGMAP_SPMI
help
  This enables a thermal sysfs driver for Qualcomm plug-and-play (QPNP)

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Re: [PATCH v2 2/5] clk: qcom: Add IPQ4019 Global Clock Controller support

[kbuild test robot]

Hi Varadarajan,

[auto build test WARNING on: robh/for-next]
[also build test WARNING on: v4.4-rc1 next-20151116]

url:
https://github.com/0day-ci/linux/commits/Matthew-McClintock/pinctrl-qcom-ipq4019-Add-IPQ4019-pinctrl-support/20151117-050512
base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux for-next
config: x86_64-allmodconfig (attached as .config)
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64 

All warnings (new ones prefixed by >>):

   drivers/clk/qcom/gcc-ipq4019.c: In function 'gcc_ipq4019_probe':
>> drivers/clk/qcom/gcc-ipq4019.c:1329:17: warning: unused variable 'dev' 
>> [-Wunused-variable]
 struct device *dev = >dev;
^

vim +/dev +1329 drivers/clk/qcom/gcc-ipq4019.c

  1313  static const struct qcom_cc_desc gcc_ipq4019_desc = {
  1314  .config = _ipq4019_regmap_config,
  1315  .clks = gcc_ipq4019_clocks,
  1316  .num_clks = ARRAY_SIZE(gcc_ipq4019_clocks),
  1317  .resets = gcc_ipq4019_resets,
  1318  .num_resets = ARRAY_SIZE(gcc_ipq4019_resets),
  1319  };
  1320  
  1321  static const struct of_device_id gcc_ipq4019_match_table[] = {
  1322  { .compatible = "qcom,gcc-ipq4019" },
  1323  { }
  1324  };
  1325  MODULE_DEVICE_TABLE(of, gcc_ipq4019_match_table);
  1326  
  1327  static int gcc_ipq4019_probe(struct platform_device *pdev)
  1328  {
> 1329  struct device *dev = >dev;
  1330  
  1331  
  1332  return qcom_cc_probe(pdev, _ipq4019_desc);
  1333  }
  1334  
  1335  static struct platform_driver gcc_ipq4019_driver = {
  1336  .probe  = gcc_ipq4019_probe,
  1337  .driver = {

---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all   Intel Corporation


.config.gz
Description: Binary data

[PATCH v2 1/5] pinctrl: qcom: ipq4019: Add IPQ4019 pinctrl support

[Matthew McClintock]

From: Varadarajan Narayanan 

Add pinctrl driver support for IPQ4019 platform

Signed-off-by: Sricharan R 
Signed-off-by: Mathieu Olivari 
Signed-off-by: Varadarajan Narayanan 
Signed-off-by: Matthew McClintock 
---

v2 - add a note in the device tree binding about the TLMM block

 .../bindings/pinctrl/qcom,ipq4019-pinctrl.txt  |  119 ++
 drivers/pinctrl/qcom/Kconfig   |8 +
 drivers/pinctrl/qcom/Makefile  |1 +
 drivers/pinctrl/qcom/pinctrl-ipq4019.c | 1280 
 4 files changed, 1408 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt
 create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq4019.c

diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt 
b/Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt
new file mode 100644
index 000..ba8a2c6
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt
@@ -0,0 +1,119 @@
+Qualcomm Atheros IPQ4019 TLMM block
+
+This is the Top Level Mode Multiplexor block found on the Qualcomm IPQ8019
+platform, it provides pinctrl, pinmux, pinconf, and gpiolib facilities.
+
+Required properties:
+- compatible: "qcom,ipq4019-pinctrl"
+- reg: Should be the base address and length of the TLMM block.
+- interrupts: Should be the parent IRQ of the TLMM block.
+- interrupt-controller: Marks the device node as an interrupt controller.
+- #interrupt-cells: Should be two.
+- gpio-controller: Marks the device node as a GPIO controller.
+- #gpio-cells : Should be two.
+The first cell is the gpio pin number and the
+second cell is used for optional parameters.
+
+Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
+a general description of GPIO and interrupt bindings.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+The pin configuration nodes act as a container for an abitrary number of
+subnodes. Each of these subnodes represents some desired configuration for a
+pin, a group, or a list of pins or groups. This configuration can include the
+mux function to select on those pin(s)/group(s), and various pin configuration
+parameters, such as pull-up, drive strength, etc.
+
+The name of each subnode is not important; all subnodes should be enumerated
+and processed purely based on their content.
+
+Each subnode only affects those parameters that are explicitly listed. In
+other words, a subnode that lists a mux function but no pin configuration
+parameters implies no information about any pin configuration parameters.
+Similarly, a pin subnode that describes a pullup parameter implies no
+information about e.g. the mux function.
+
+
+The following generic properties as defined in pinctrl-bindings.txt are valid
+to specify in a pin configuration subnode:
+ pins, function, bias-disable, bias-pull-down, bias-pull,up, drive-strength.
+
+Non-empty subnodes must specify the 'pins' property.
+Note that not all properties are valid for all pins.
+
+
+Valid values for qcom,pins are:
+  gpio0-gpio70
+Supports mux, bias and drive-strength
+
+sdio_cd, sdio_clk, sdio_cmd, sdio_data1, sdio_data1, sdio_data1, 
sdio_data1,
+sdio_data5, sdio_data6, sdio_data7
+
+Valid values for qcom,function are:
+smart0, jtag, audio0, mdio0, wcss0_dbg18, wcss1_dbg18, qdss_tracedata_a, mdc,
+wcss0_dbg19, wcss1_dbg19, blsp_uart1, wifi0_uart, wifi1_uart, smart1,
+wcss0_dbg20, wcss1_dbg20, wifi0_uart0, wifi1_uart0, wcss0_dbg21, wcss1_dbg21,
+blsp_i2c0, wcss0_dbg22, wcss1_dbg22, wcss0_dbg23, wcss1_dbg23, blsp_i2c1,
+wcss0_dbg24, wcss1_dbg24, wcss0_dbg25, wcss1_dbg25, pcie_rst, wcss0_dbg26,
+wcss1_dbg26, pcie_clk0, wcss0_dbg27, wcss1_dbg27, led0, blsp_uart0, led1,
+chip_irq0, wifi0_uart1, wifi1_uart1, wcss0_dbg28, wcss1_dbg28, chip_rst,
+audio_spdifout, sdio1, rgmii2, sdio2, rgmii3, sdio3, rgmii_rx, sdio_clk,
+wcss0_dbg29, wcss1_dbg29, wcss0_dbg16, wcss1_dbg16, audio1, wcss0_dbg17,
+wcss1_dbg17, sdio_cd, rgmii0, sdio0, rgmii1, rgmii_txc, audio_td1, sdio_cmd,
+audio_td2, sdio4, audio_td3, sdio5, audio_pwm0, sdio6, audio_pwm1, sdio7,
+rgmii_rxc, audio_pwm2, rgmii_tx, audio_pwm3, wcss0_dbg30, wcss1_dbg30,
+wcss0_dbg31, wcss1_dbg31, rmii00, led2, rmii01, wifi0_wci, wifi1_wci,
+rmii0_tx, rmii0_rx, pcie_clk1, led3, pcie_wakeup, rmii0_refclk,
+wifi0_rfsilient0, wifi1_rfsilient0, smart2, led4, wifi0_cal, wifi1_cal,
+wifi_wci0, rmii0_dv, wifi_wci1, rmii1_refclk, blsp_spi1, led5, rmii10,
+blsp_spi0, led6, rmii11, led7, rmii1_dv, led8, rmii1_tx, aud_pin, led9,
+rmii1_rx, led10, wifi0_rfsilient1, wifi1_rfsilient1, led11, qpic_pad,
+qdss_cti_trig_in_a0, mdio1, audio2, dbg_out, wcss0_dbg, wcss1_dbg, atest_char3,

[PATCH v2 4/5] qcom: ipq4019: Add basic board/dts support for IPQ4019 SoC

[Matthew McClintock]

From: Matthew McClintock 

Add initial dts files and SoC support for IPQ4019

Signed-off-by: Varadarajan Narayanan 
---

v2 - add sleep_clk

 arch/arm/boot/dts/qcom-ipq4019.dtsi | 115 
 1 file changed, 115 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019.dtsi

diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
new file mode 100644
index 000..fc73822
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "skeleton.dtsi"
+#include 
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019";
+   compatible = "qcom,ipq4019";
+   interrupt-parent = <>;
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   cpu@0 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a7";
+   reg = <0x0>;
+   clocks = < GCC_APPS_CLK_SRC>;
+   };
+
+   cpu@1 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a7";
+   reg = <0x1>;
+   clocks = < GCC_APPS_CLK_SRC>;
+   };
+
+   cpu@2 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a7";
+   reg = <0x2>;
+   clocks = < GCC_APPS_CLK_SRC>;
+   };
+
+   cpu@3 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a7";
+   reg = <0x3>;
+   clocks = < GCC_APPS_CLK_SRC>;
+   };
+   };
+
+   clocks {
+   sleep_clk: sleep_clk {
+   compatible = "fixed-clock";
+   clock-frequency = <32768>;
+   #clock-cells = <0>;
+   };
+   };
+
+   soc {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+   compatible = "simple-bus";
+
+   intc: interrupt-controller@b00 {
+   compatible = "qcom,msm-qgic2";
+   interrupt-controller;
+   #interrupt-cells = <3>;
+   reg = <0x0b00 0x1000>,
+   <0x0b002000 0x1000>;
+   };
+
+   gcc: clock-controller@180 {
+   compatible = "qcom,gcc-ipq4019";
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+   reg = <0x180 0x6>;
+   };
+
+   tlmm: pinctrl@0x0100 {
+   compatible = "qcom,ipq4019-pinctrl";
+   reg = <0x0100 0x30>;
+   gpio-controller;
+   #gpio-cells = <2>;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   interrupts = <0 208 0>;
+   };
+
+   serial@78af000 {
+   compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+   reg = <0x78af000 0x200>;
+   interrupts = <0 107 0>;
+   status = "disabled";
+   clocks = < GCC_BLSP1_UART1_APPS_CLK>,
+   < GCC_BLSP1_AHB_CLK>;
+   clock-names = "core", "iface";
+   };
+
+   serial@78b {
+   compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+   reg = <0x78b 0x200>;
+   interrupts = <0 108 0>;
+   status = "disabled";
+   clocks = < GCC_BLSP1_UART2_APPS_CLK>,
+   < GCC_BLSP1_AHB_CLK>;
+   clock-names = "core", "iface";
+   };
+   };
+};
-- 
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a Linux Foundation Collaborative Project

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[PATCH v2 5/5] dts: ipq4019: Add support for IPQ4019 DK01 board

[Matthew McClintock]

From: Matthew McClintock 

Initial board support dts files for DK01 board.

Signed-off-by: Senthilkumar N L 
Signed-off-by: Varadarajan Narayanan 
---

v2 - add xo clock

 arch/arm/boot/dts/Makefile  |  1 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts | 22 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi   | 59 +
 3 files changed, 82 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 30bbc37..11b151e 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -505,6 +505,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-apq8074-dragonboard.dtb \
qcom-apq8084-ifc6540.dtb \
qcom-apq8084-mtp.dtb \
+   qcom-ipq4019-ap.dk01.1-c1.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
new file mode 100644
index 000..0d92f1b
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
@@ -0,0 +1,22 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "qcom-ipq4019-ap.dk01.1.dtsi"
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK01.1-C1";
+
+};
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
new file mode 100644
index 000..fe78f3f
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -0,0 +1,59 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "qcom-ipq4019.dtsi"
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1";
+   compatible = "qcom,ipq4019";
+
+   clocks {
+xo: xo {
+compatible = "fixed-clock";
+clock-frequency = <4800>;
+#clock-cells = <0>;
+};
+   };
+
+   soc {
+
+
+   timer {
+   compatible = "arm,armv7-timer";
+   interrupts = <1 2 0xf08>,
+<1 3 0xf08>,
+<1 4 0xf08>,
+<1 1 0xf08>;
+   clock-frequency = <4800>;
+   };
+
+   pinctrl@0x0100 {
+   serial_pins: serial_pinmux {
+   mux {
+   pins = "gpio60", "gpio61";
+   function = "blsp_uart0";
+   bias-disable;
+   };
+   };
+   };
+
+   serial@78af000 {
+   pinctrl-0 = <_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+   };
+};
-- 
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[PATCH v2 2/5] clk: qcom: Add IPQ4019 Global Clock Controller support

[Matthew McClintock]

From: Varadarajan Narayanan 

This patch adds support for the global clock controller found on
the IPQ4019 based devices. This includes UART, I2C, SPI etc.

Signed-off-by: Pradeep Banavathi 
Signed-off-by: Senthilkumar N L 
Signed-off-by: Varadarajan Narayanan 
Signed-off-by: Matthew McClintock 
---

v2 - drop calls qcom_cc_remove, gcc_ipq4019_remove
   - move defines into clk structs
   - remove src,cfg in struct initializations
   - make hex values lowercase
   - clean up MODULE_ALIAS and MODULE_DESCRIPTION
   - change tabs after define to spacein dt include files
   - remove extra AUDIO_BLK_ARES define
   - remove unneeded of_match_device from gcc_ipq4019_probe
   - move sleep_clk and xo to soc and board level dts
   - drop all the (not required) fixed-clocks for now
   - combine reset dts include files into one overall dts include

 .../devicetree/bindings/clock/qcom,gcc.txt |1 +
 drivers/clk/qcom/Kconfig   |9 +
 drivers/clk/qcom/Makefile  |1 +
 drivers/clk/qcom/gcc-ipq4019.c | 1358 
 include/dt-bindings/clock/qcom,gcc-ipq4019.h   |  158 +++
 5 files changed, 1527 insertions(+)
 create mode 100644 drivers/clk/qcom/gcc-ipq4019.c
 create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq4019.h

diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt 
b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
index 152dfaa..4c98ab3 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
@@ -7,6 +7,7 @@ Required properties :
"qcom,gcc-apq8064"
"qcom,gcc-apq8084"
"qcom,gcc-ipq8064"
+   "qcom,gcc-ipq4019"
"qcom,gcc-msm8660"
"qcom,gcc-msm8916"
"qcom,gcc-msm8960"
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index ee4c83a..085fc17 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -28,6 +28,15 @@ config APQ_MMCC_8084
  Say Y if you want to support multimedia devices such as display,
  graphics, video encode/decode, camera, etc.
 
+config IPQ_GCC_4019
+   tristate "IPQ4019 Global Clock Controller"
+   depends on COMMON_CLK_QCOM
+   help
+ Support for the global clock controller on ipq4019 devices.
+ Say Y if you want to use peripheral devices such as UART, SPI,
+ i2c, USB, SD/eMMC, etc.
+
+
 config IPQ_GCC_806X
tristate "IPQ806x Global Clock Controller"
depends on COMMON_CLK_QCOM
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index fe62523..c88d92f 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -13,6 +13,7 @@ clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o
 
 obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o
 obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o
+obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o
 obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
 obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
 obj-$(CONFIG_MSM_GCC_8660) += gcc-msm8660.o
diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers/clk/qcom/gcc-ipq4019.c
new file mode 100644
index 000..a2bbb91
--- /dev/null
+++ b/drivers/clk/qcom/gcc-ipq4019.c
@@ -0,0 +1,1358 @@
+/*
+ * Copyright (c) 2015 The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#include "common.h"
+#include "clk-regmap.h"
+#include "clk-rcg.h"
+#include "clk-branch.h"
+#include "reset.h"
+
+enum {
+   P_XO,
+   P_FEPLL200,
+   P_FEPLL500,
+   P_DDRPLL,
+   P_FEPLLWCSS2G,
+   P_FEPLLWCSS5G,
+   P_FEPLL125DLY,
+   P_DDRPLLAPSS,
+};
+
+static struct parent_map gcc_xo_200_500_map[] = {
+   { P_XO, 0 },
+   { P_FEPLL200, 1 },
+   { P_FEPLL500, 2 },
+};
+
+static const char * const gcc_xo_200_500[] = {
+   "xo",
+   "fepll200",
+   "fepll500",
+};
+
+static struct parent_map gcc_xo_200_map[] = {
+   {  P_XO, 0 },
+   {  P_FEPLL200, 1 },
+};
+
+static const char * const gcc_xo_200[] = {
+   "xo",
+   "fepll200",
+};
+
+static struct parent_map gcc_xo_200_spi_map[] = {
+   {  P_XO, 0 },
+   {  P_FEPLL200, 2 },
+};
+
+static const char * const 

[PATCH v3 2/5] clk: qcom: Add IPQ4019 Global Clock Controller support

[Matthew McClintock]

From: Varadarajan Narayanan 

This patch adds support for the global clock controller found on
the IPQ4019 based devices. This includes UART, I2C, SPI etc.

Signed-off-by: Pradeep Banavathi 
Signed-off-by: Senthilkumar N L 
Signed-off-by: Varadarajan Narayanan 
Signed-off-by: Matthew McClintock 
---

v2:
- drop calls qcom_cc_remove, gcc_ipq4019_remove
- move defines into clk structs
- remove src,cfg in struct initializations
- make hex values lowercase
- clean up MODULE_ALIAS and MODULE_DESCRIPTION
- change tabs after define to spacein dt include files
- remove extra AUDIO_BLK_ARES define
- remove unneeded of_match_device from gcc_ipq4019_probe
- move sleep_clk and xo to soc and board level dts
- drop all the (not required) fixed-clocks for now
- combine reset dts include files into one overall dts include

v3:
- fix unused variable from refactored code

 .../devicetree/bindings/clock/qcom,gcc.txt |1 +
 drivers/clk/qcom/Kconfig   |9 +
 drivers/clk/qcom/Makefile  |1 +
 drivers/clk/qcom/gcc-ipq4019.c | 1355 
 include/dt-bindings/clock/qcom,gcc-ipq4019.h   |  158 +++
 5 files changed, 1524 insertions(+)
 create mode 100644 drivers/clk/qcom/gcc-ipq4019.c
 create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq4019.h

diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt 
b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
index 152dfaa..4c98ab3 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
@@ -7,6 +7,7 @@ Required properties :
"qcom,gcc-apq8064"
"qcom,gcc-apq8084"
"qcom,gcc-ipq8064"
+   "qcom,gcc-ipq4019"
"qcom,gcc-msm8660"
"qcom,gcc-msm8916"
"qcom,gcc-msm8960"
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index ee4c83a..085fc17 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -28,6 +28,15 @@ config APQ_MMCC_8084
  Say Y if you want to support multimedia devices such as display,
  graphics, video encode/decode, camera, etc.
 
+config IPQ_GCC_4019
+   tristate "IPQ4019 Global Clock Controller"
+   depends on COMMON_CLK_QCOM
+   help
+ Support for the global clock controller on ipq4019 devices.
+ Say Y if you want to use peripheral devices such as UART, SPI,
+ i2c, USB, SD/eMMC, etc.
+
+
 config IPQ_GCC_806X
tristate "IPQ806x Global Clock Controller"
depends on COMMON_CLK_QCOM
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index fe62523..c88d92f 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -13,6 +13,7 @@ clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o
 
 obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o
 obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o
+obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o
 obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
 obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
 obj-$(CONFIG_MSM_GCC_8660) += gcc-msm8660.o
diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers/clk/qcom/gcc-ipq4019.c
new file mode 100644
index 000..21def7f
--- /dev/null
+++ b/drivers/clk/qcom/gcc-ipq4019.c
@@ -0,0 +1,1355 @@
+/*
+ * Copyright (c) 2015 The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#include "common.h"
+#include "clk-regmap.h"
+#include "clk-rcg.h"
+#include "clk-branch.h"
+#include "reset.h"
+
+enum {
+   P_XO,
+   P_FEPLL200,
+   P_FEPLL500,
+   P_DDRPLL,
+   P_FEPLLWCSS2G,
+   P_FEPLLWCSS5G,
+   P_FEPLL125DLY,
+   P_DDRPLLAPSS,
+};
+
+static struct parent_map gcc_xo_200_500_map[] = {
+   { P_XO, 0 },
+   { P_FEPLL200, 1 },
+   { P_FEPLL500, 2 },
+};
+
+static const char * const gcc_xo_200_500[] = {
+   "xo",
+   "fepll200",
+   "fepll500",
+};
+
+static struct parent_map gcc_xo_200_map[] = {
+   {  P_XO, 0 },
+   {  P_FEPLL200, 1 },
+};
+
+static const char * const gcc_xo_200[] = {
+   "xo",
+   "fepll200",
+};
+
+static struct parent_map gcc_xo_200_spi_map[] = {
+   {  P_XO, 0 },
+   {  P_FEPLL200, 2 },
+};
+
+static const char 

Re: [PATCH v2 1/5] pinctrl: qcom: ipq4019: Add IPQ4019 pinctrl support

[Rob Herring]

On Mon, Nov 16, 2015 at 03:02:01PM -0600, Matthew McClintock wrote:
> From: Varadarajan Narayanan 
> 
> Add pinctrl driver support for IPQ4019 platform
> 
> Signed-off-by: Sricharan R 
> Signed-off-by: Mathieu Olivari 
> Signed-off-by: Varadarajan Narayanan 
> Signed-off-by: Matthew McClintock 
> ---
> 
> v2 - add a note in the device tree binding about the TLMM block

Acked-by: Rob Herring 

> 
>  .../bindings/pinctrl/qcom,ipq4019-pinctrl.txt  |  119 ++
>  drivers/pinctrl/qcom/Kconfig   |8 +
>  drivers/pinctrl/qcom/Makefile  |1 +
>  drivers/pinctrl/qcom/pinctrl-ipq4019.c | 1280 
> 
>  4 files changed, 1408 insertions(+)
>  create mode 100644 
> Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt
>  create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq4019.c
> 
> diff --git 
> a/Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt 
> b/Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt
> new file mode 100644
> index 000..ba8a2c6
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt
> @@ -0,0 +1,119 @@
> +Qualcomm Atheros IPQ4019 TLMM block
> +
> +This is the Top Level Mode Multiplexor block found on the Qualcomm IPQ8019
> +platform, it provides pinctrl, pinmux, pinconf, and gpiolib facilities.
> +
> +Required properties:
> +- compatible: "qcom,ipq4019-pinctrl"
> +- reg: Should be the base address and length of the TLMM block.
> +- interrupts: Should be the parent IRQ of the TLMM block.
> +- interrupt-controller: Marks the device node as an interrupt controller.
> +- #interrupt-cells: Should be two.
> +- gpio-controller: Marks the device node as a GPIO controller.
> +- #gpio-cells : Should be two.
> +The first cell is the gpio pin number and the
> +second cell is used for optional parameters.
> +
> +Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt 
> for
> +a general description of GPIO and interrupt bindings.
> +
> +Please refer to pinctrl-bindings.txt in this directory for details of the
> +common pinctrl bindings used by client devices, including the meaning of the
> +phrase "pin configuration node".
> +
> +The pin configuration nodes act as a container for an abitrary number of
> +subnodes. Each of these subnodes represents some desired configuration for a
> +pin, a group, or a list of pins or groups. This configuration can include the
> +mux function to select on those pin(s)/group(s), and various pin 
> configuration
> +parameters, such as pull-up, drive strength, etc.
> +
> +The name of each subnode is not important; all subnodes should be enumerated
> +and processed purely based on their content.
> +
> +Each subnode only affects those parameters that are explicitly listed. In
> +other words, a subnode that lists a mux function but no pin configuration
> +parameters implies no information about any pin configuration parameters.
> +Similarly, a pin subnode that describes a pullup parameter implies no
> +information about e.g. the mux function.
> +
> +
> +The following generic properties as defined in pinctrl-bindings.txt are valid
> +to specify in a pin configuration subnode:
> + pins, function, bias-disable, bias-pull-down, bias-pull,up, drive-strength.
> +
> +Non-empty subnodes must specify the 'pins' property.
> +Note that not all properties are valid for all pins.
> +
> +
> +Valid values for qcom,pins are:
> +  gpio0-gpio70
> +Supports mux, bias and drive-strength
> +
> +sdio_cd, sdio_clk, sdio_cmd, sdio_data1, sdio_data1, sdio_data1, 
> sdio_data1,
> +sdio_data5, sdio_data6, sdio_data7
> +
> +Valid values for qcom,function are:
> +smart0, jtag, audio0, mdio0, wcss0_dbg18, wcss1_dbg18, qdss_tracedata_a, mdc,
> +wcss0_dbg19, wcss1_dbg19, blsp_uart1, wifi0_uart, wifi1_uart, smart1,
> +wcss0_dbg20, wcss1_dbg20, wifi0_uart0, wifi1_uart0, wcss0_dbg21, wcss1_dbg21,
> +blsp_i2c0, wcss0_dbg22, wcss1_dbg22, wcss0_dbg23, wcss1_dbg23, blsp_i2c1,
> +wcss0_dbg24, wcss1_dbg24, wcss0_dbg25, wcss1_dbg25, pcie_rst, wcss0_dbg26,
> +wcss1_dbg26, pcie_clk0, wcss0_dbg27, wcss1_dbg27, led0, blsp_uart0, led1,
> +chip_irq0, wifi0_uart1, wifi1_uart1, wcss0_dbg28, wcss1_dbg28, chip_rst,
> +audio_spdifout, sdio1, rgmii2, sdio2, rgmii3, sdio3, rgmii_rx, sdio_clk,
> +wcss0_dbg29, wcss1_dbg29, wcss0_dbg16, wcss1_dbg16, audio1, wcss0_dbg17,
> +wcss1_dbg17, sdio_cd, rgmii0, sdio0, rgmii1, rgmii_txc, audio_td1, sdio_cmd,
> +audio_td2, sdio4, audio_td3, sdio5, audio_pwm0, sdio6, audio_pwm1, sdio7,
> +rgmii_rxc, audio_pwm2, rgmii_tx, audio_pwm3, wcss0_dbg30, wcss1_dbg30,
> +wcss0_dbg31, wcss1_dbg31, rmii00, led2, rmii01, wifi0_wci, wifi1_wci,
> +rmii0_tx, rmii0_rx, pcie_clk1, led3, pcie_wakeup, rmii0_refclk,
> +wifi0_rfsilient0, wifi1_rfsilient0, smart2, led4, 

Re: [PATCH v2] mmc: sdhci-msm: Boost controller core clock

[Ulf Hansson]

[...]

>> Ahh, I see.
>>
>> It seems like a reasonable assumption that the controller can't cope
>> with a higher clock rate than 100 MHz as "input" clock. That would
>> then mean that there are different versions of the controller, as it
>> seems like for some version it's fine with 200MHz and for some 100MHz.
>>
>> According to the DT compatible strings, *one* version is currently
>> supported, "qcom,sdhci-msm-v4"...
>
> The same version of hardware is there 4 times. The difference is
> the maximum clock frequency supported by them is different. In
> downstream kernels we've handled this by trimming the frequency
> tables for the different controllers in the clock driver.
> Setting the clock to INT_MAX will make it run at 400MHz, which
> doesn't look to be supported by anything besides sdc1 on 8974ac.
>
>>
>> I see two viable solutions. One would be to limit the clock rate
>> depending on the version of the controller (new compatible strings
>> needs to be added). Another one would be to limit the clock rate by
>> using the existing DT binding for max-frequency, and thus do a
>> clk_set_rate(mmc->f_max) during probe.
>>
>
> I'd rather see that done via OPP tables in DT, but I suppose
> max-frequency is fine too. We'll need to use OPPs soon enough
> because there's a voltage associated with that frequency.

Okay, thanks for sharing the details.

>
> In case you're wondering, the max frequency for sdc1 on 8974ac is
> 400MHz. If it's just a plain 8974pro then the max frequency is
> 200MHz. Otherwise, sdc2 maxes out at 200Mhz and sdc3 and sdc4 max
> out at 100MHz.

When you say that sdc1 supports 400MHz, what does that mean? That it
actually can cope with that clock rate when communicating with the MMC
card?

This makes me wonder how you deal with power management (DVFS).

For example when you have the possibility to gate this clock (at
request inactivity) when the rate is set to 400 MHz and OPP is
increased, how will then that clock gating affect the OPP?

Kind regards
Uffe
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Re: [PATCH] Revert "thermal: qcom_spmi: allow compile test"

[Eduardo Valentin]

On Mon, Nov 16, 2015 at 10:43:50PM +0100, Arnd Bergmann wrote:
> This just caused build errors:
> 
> warning: (QCOM_SPMI_TEMP_ALARM) selects REGMAP_SPMI which has unmet direct 
> dependencies (SPMI)
> drivers/built-in.o: In function `regmap_spmi_ext_gather_write':
> :(.text+0x609b0): undefined reference to `spmi_ext_register_write'
> :(.text+0x609f0): undefined reference to `spmi_ext_register_writel'
> 
> While it's generally a good idea to allow compile testing, in this
> case, it just doesn't work, so reverting the patch that
> introduced the compile-test variant seems the most appropriate
> solution.

Looking this closer, the original patch simply does not make sense. The
platform dependent code is already covered by the SPMI code.

> 
> Note that SPIMI also has a 'depends on ARCH_QCOM || COMPILE_TEST'
> statement, so we should be able to enable SPMI on all architectures
> for compile testing already.

So, applied. I just s/SPIMI/SPMI/g.

> 
> Signed-off-by: Arnd Bergmann 
> Fixes: cb7fb4d34202 ("thermal: qcom_spmi: allow compile test")
> 
> diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
> index 2e7524f0f3f7..6045b17d0e00 100644
> --- a/drivers/thermal/Kconfig
> +++ b/drivers/thermal/Kconfig
> @@ -381,7 +381,7 @@ endmenu
>  
>  config QCOM_SPMI_TEMP_ALARM
>   tristate "Qualcomm SPMI PMIC Temperature Alarm"
> - depends on OF && (SPMI || COMPILE_TEST) && IIO
> + depends on OF && SPMI && IIO
>   select REGMAP_SPMI
>   help
> This enables a thermal sysfs driver for Qualcomm plug-and-play (QPNP)
> 
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RE: [PATCH] ARM: use "depends on" for SoC configs instead of "if" after prompt

[yamada.masahiro]

Hi Arnd,

 
> On Monday 16 November 2015 12:06:10 Masahiro Yamada wrote:
> > Many ARM sub-architectures use prompts followed by "if" conditional,
> > but it is wrong.
> >
> > Please notice the difference between
> >
> > config ARCH_FOO
> > bool "Foo SoCs" if ARCH_MULTI_V7
> >
> > and
> >
> > config ARCH_FOO
> > bool "Foo SoCs"
> > depends on ARCH_MULTI_V7
> >
> > These two are *not* equivalent!
> >
> > In the former statement, it is not ARCH_FOO, but its prompt that
> > depends on ARCH_MULTI_V7.  So, it is completely valid that ARCH_FOO is
> > selected by another, but ARCH_MULTI_V7 is still disabled. As it is not
> > unmet dependency, Kconfig never warns.  This is probably not what you
> > want.
> 
> Did you encounter a case where someone actually did a 'select' on one of
> those symbols? I probably introduced a lot of them and did not expect that
> to happen.

No, for ARM sub-architectures.
But, yes for the ARM core part.


For example, the following entry in arch/arm/Kconfig is suspicous.

config PCI
bool "PCI support" if MIGHT_HAVE_PCI
help
  Find out whether you have a PCI motherboard. PCI is the name of a
  bus system, i.e. the way the CPU talks to the other stuff inside
  your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
  VESA. If you have PCI, say Y, otherwise N.




Try "make ARCH=arm footbridge_defconfig" and check the .config file.

It defines CONFIG_PCI=y, but not CONFIG_MIGHT_HAVE_PCI.
I am not sure this is a sane .config or not.

But, anyway, Kconfig does not complain about it.


We have similar issues for CPU_V6, CPU_V6K, CPU_V7, etc.
The config is selected, but the "if" conditional is unmet.
(I decided to postpone this problem because it would take some time to 
understand
complicated dependency.)

The use of a prompt followed by "if" without correct understanding is dangerous
because it could hide the unmet dependency problem.

I want to eliminate the potential problem by this patch
before somebody introduce insane dependency.


> 
> > diff --git a/arch/arm/mach-integrator/Kconfig
> > b/arch/arm/mach-integrator/Kconfig
> > index 02d0834..2fa9d11 100644
> > --- a/arch/arm/mach-integrator/Kconfig
> > +++ b/arch/arm/mach-integrator/Kconfig
> > @@ -1,5 +1,6 @@
> >  config ARCH_INTEGRATOR
> > -   bool "ARM Ltd. Integrator family" if (ARCH_MULTI_V4T ||
> ARCH_MULTI_V5 || ARCH_MULTI_V6)
> > +   bool "ARM Ltd. Integrator family"
> > +   depends on ARCH_MULTI_V4T || ARCH_MULTI_V5 || ARCH_MULTI_V6
> > select ARM_AMBA
> > select ARM_PATCH_PHYS_VIRT if MMU
> > select AUTO_ZRELADDR
> 
> There is one related change that I would like to see, and that is to convert
> all top-level 'config' statements that have sub-options into 'menuconfig'
> statements for consistency. At the moment, the platform menu has a mix of
> platform-selection and platform-specific options, and I'd like to make that
> more consistent.

I agree, but in another patch (or series)?



Best Regards
Mashairo Yamada

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Re: [PATCH] ARM: use "depends on" for SoC configs instead of "if" after prompt

[Russell King - ARM Linux]

On Mon, Nov 16, 2015 at 10:32:51AM +, yamada.masah...@socionext.com wrote:
> Hi Arnd,
> 
>  
> > On Monday 16 November 2015 12:06:10 Masahiro Yamada wrote:
> > > Many ARM sub-architectures use prompts followed by "if" conditional,
> > > but it is wrong.
> > >
> > > Please notice the difference between
> > >
> > > config ARCH_FOO
> > > bool "Foo SoCs" if ARCH_MULTI_V7
> > >
> > > and
> > >
> > > config ARCH_FOO
> > > bool "Foo SoCs"
> > > depends on ARCH_MULTI_V7
> > >
> > > These two are *not* equivalent!
> > >
> > > In the former statement, it is not ARCH_FOO, but its prompt that
> > > depends on ARCH_MULTI_V7.  So, it is completely valid that ARCH_FOO is
> > > selected by another, but ARCH_MULTI_V7 is still disabled. As it is not
> > > unmet dependency, Kconfig never warns.  This is probably not what you
> > > want.
> > 
> > Did you encounter a case where someone actually did a 'select' on one of
> > those symbols? I probably introduced a lot of them and did not expect that
> > to happen.
> 
> No, for ARM sub-architectures.
> But, yes for the ARM core part.
> 
> 
> For example, the following entry in arch/arm/Kconfig is suspicous.
> 
> config PCI
> bool "PCI support" if MIGHT_HAVE_PCI
> help
>   Find out whether you have a PCI motherboard. PCI is the name of a
>   bus system, i.e. the way the CPU talks to the other stuff inside
>   your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
>   VESA. If you have PCI, say Y, otherwise N.
> 
> 
> 
> 
> Try "make ARCH=arm footbridge_defconfig" and check the .config file.
> 
> It defines CONFIG_PCI=y, but not CONFIG_MIGHT_HAVE_PCI.
> I am not sure this is a sane .config or not.

It's correct.  "MIGHT_HAVE_PCI" is used by platforms which _might_ _have_
_PCI_, not by platforms which _do_ _have_ _PCI_.  Platforms which _do_
_have_ _PCI_ select PCI directly, and because "MIGHT_HAVE_PCI" is not
set, users are not offered an option that they can never disable.

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