On 07/23/14 09:05, Ivan T. Ivanov wrote:
>
>> both on
>>> pm8xxx and qpnp-pin there are two different HW blocks, one for GPIO and one
>>> for
>>> MPP. And if you look in your pinconf_set function you will see that they are
>>> very different.
> I bet that the hardware blocks are almost identical,
On 07/18/14 13:53, Srinivas Kandagatla wrote:
>
> @@ -468,6 +473,11 @@ static void mmci_dma_setup(struct mmci_host *host)
> if (max_seg_size < host->mmc->max_seg_size)
> host->mmc->max_seg_size = max_seg_size;
> }
> +
> + if (variant->qcom_dml && host->
On 07/23/14 13:28, Siteshwar wrote:
> Hello,
>
> I am trying to set RTC on Nexus 5 (which uses qpnp-rtc driver).and
> getting a permission error while setting it.
>
> I am making following call from my application with valid arguments :
>
> ioctl(rtc_fd, RTC_SET_TIME, tod)
>
> when I make this call
On 07/23/14 03:26, Kiran Padwal wrote:
> Make of_device_id array const, because all OF functions handle it as const.
>
> Signed-off-by: Kiran Padwal
> ---
Acked-by: Stephen Boyd
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Found
On 07/22/14 14:46, Bjorn Andersson wrote:
> For pm8941 the valid power supply values are:
> GPIO 1-14
>0: VPH
>2: SMPS3
>3: LDO6
>
> GPIO 15-18
> 2: SMPS3
> 3: LDO6
>
> GPIO 19-36
> 0: VPH
> 1: VDD_TORCH
> 2: SPMS3
> 3: LDO6
>
> MPP 1-8
> 0: VPH
> 1: LDO1
> 2: SPMS
On 07/24/14 08:40, Linus Walleij wrote:
> On Thu, Jul 24, 2014 at 1:47 AM, Stephen Boyd wrote:
>
>>> Please add these constants to the table of valid power-source values and use
>>> something like I did to translate them to register values - it makes the DT
>>> mu
On 07/28, Kumar Gala wrote:
>
> On Jul 21, 2014, at 4:26 PM, Stephen Boyd wrote:
>
> > Hi Mike,
> >
> > The following changes since commit a497c3ba1d97fc69c1e78e7b96435ba8c2cb42ee:
> >
> > Linux 3.16-rc2 (2014-06-21 19:02:54 -1000)
> >
eij
> Signed-off-by: Srinivas Kandagatla
>
Reviewed-by: Stephen Boyd
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation
--
To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in
the body of a message
On 07/29/14 16:45, Grant Likely wrote:
> On Tue, 29 Jul 2014 17:06:42 +0300, Stanimir Varbanov
> wrote:
>>
>> This was just an example. Of course it has many issues and probaly it is
>> wrong:) The main goal was to understand does IORESOURCE_REG resource
>> type and parsing the *reg* properties f
On 07/29, Rob Herring wrote:
> On Tue, Jul 29, 2014 at 8:07 PM, Stephen Boyd wrote:
> > On 07/29/14 16:45, Grant Likely wrote:
> >> On Tue, 29 Jul 2014 17:06:42 +0300, Stanimir Varbanov
> >> wrote:
> >>>
> >>> This was just an example. Of cour
olas Pitre
Signed-off-by: Stephen Boyd
---
drivers/irqchip/irq-gic.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 7c131cf7cc13..824c1e2ac403 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.
On 08/04/14 16:20, Nicolas Pitre wrote:
> On Mon, 4 Aug 2014, Stephen Boyd wrote:
>
>> diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
>> index 7c131cf7cc13..824c1e2ac403 100644
>> --- a/drivers/irqchip/irq-gic.c
>> +++ b/drivers/irqchip/irq-gic
lock around event 2 and before
event 3. Use smp_mb__after_unlock_lock() before event 3 to ensure
that event 1 is seen before event 3 on other CPUs that may be
executing event 2.
Signed-off-by: Stephen Boyd
---
Changes since v1:
* Move gic_sgi_lock definition below gic_cpu_map[]
* Just use spinlo
Kannan (1):
msm: scm: Add API to query for service/command availability.
Stephen Boyd (5):
msm: scm: Fix incorrect cache invalidation
msm: scm: Get cacheline size from CTR
msm: scm: Add atomic SCM APIs
msm: scm: Add a feat version query API
msm: scm: Move the scm driver to drivers/soc/qcom
Some users of SCM need to detect features and also detect if
those features have certain versions available. Add this API.
Signed-off-by: Stephen Boyd
---
arch/arm/mach-qcom/scm.c | 13 +
arch/arm/mach-qcom/scm.h | 1 +
2 files changed, 14 insertions(+)
diff --git a/arch/arm/mach
]() functions
corresponding to the number of arguments passed.
Signed-off-by: Stephen Boyd
---
arch/arm/mach-qcom/scm.c | 73
arch/arm/mach-qcom/scm.h | 5 +++-
2 files changed, 77 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-qcom/scm.c b
scm call allowing us to easily determine what caused the error
to occur.
Signed-off-by: Olav Haugan
Signed-off-by: Stephen Boyd
---
arch/arm/mach-qcom/scm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-qcom/scm.c b/arch/arm/mach-qcom/scm.c
index 7c62c03324f4..cfd4717aec78
On 08/04/14 17:59, Frank Rowand wrote:
> Stephen,
>
> I made some changes to drivers/tty/serial/msm_serial.c to allow kgdb
> to work with the dragon board (which has a qcom,msm-uartdm-v1.4 serial
> port).
>
> I will reply to this email with the patches.
>
> With these fixes, kgdb properly communica
From: Saravana Kannan
Some drivers may need to query the secure environment about the
availability of a particular service/command. Add support for
this.
Signed-off-by: Saravana Kannan
[sb...@codeaurora.org: Add some commit text]
Signed-off-by: Stephen Boyd
---
arch/arm/mach-qcom/scm.c | 18
Architectural changes in the ARM Linux kernel tree mandate
the eventual removal of the mach-* directories. Move the
scm driver to drivers/soc/qcom and the scm header to
include/soc/qcom to support that removal.
Signed-off-by: Stephen Boyd
---
arch/arm/mach-qcom/Kconfig | 3
e size aligned so make sure to invalidate the last
few bytes in such situations. It also doesn't do anything about
outer caches so make sure to invalidate and flush those as well.
Signed-off-by: Stephen Boyd
---
arch/arm/mach-qcom/scm.c | 31 +++
1 file changed, 23
flushing any
other cached buffer (being passed to the secure world) to
callers.
Signed-off-by: Vikram Mulukutla
Signed-off-by: Stephen Boyd
---
arch/arm/mach-qcom/scm.c | 17 -
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-qcom/scm.c b/arch/arm
Instead of hardcoding the cacheline size as 32, get the cacheline
size from the CTR register.
Signed-off-by: Stephen Boyd
---
arch/arm/mach-qcom/scm.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-qcom/scm.c b/arch/arm/mach-qcom/scm.c
index
On 07/28/14 01:39, Ivan T. Ivanov wrote:
> I am working on proposal from Stephen Boyd to encode GPIO/MPP mode and
> source select into combined function. Something like this one:
>
> #define PM8XXX_DIGITAL_IN 0
> #define PM8XXX_DIGITAL_OUT1
> #define PM8
+nico (sorry dropped CC for v2)
On 08/04/14 16:27, Stephen Boyd wrote:
> Commit 1a6b69b6548c (ARM: gic: add CPU migration support,
> 2012-04-12) introduced an acquisition of the irq_controller_lock
> in gic_raise_softirq() which can lead to a spinlock recursion if
> the gic_arch_ext
On 08/04/14 19:09, Frank Rowand wrote:
> On 8/4/2014 6:33 PM, Stephen Boyd wrote:
>> On 08/04/14 17:59, Frank Rowand wrote:
>>> Stephen,
>>>
>>> I made some changes to drivers/tty/serial/msm_serial.c to allow kgdb
>>> to work with the dragon board (whi
On 08/05/14 12:50, Nicolas Pitre wrote:
> On Tue, 5 Aug 2014, Stephen Boyd wrote:
>
>> +nico (sorry dropped CC for v2)
>>
>> On 08/04/14 16:27, Stephen Boyd wrote:
>>> Commit 1a6b69b6548c (ARM: gic: add CPU migration support,
>>> 2012-04-12) introduced
On 08/05/14 12:22, Stephen Boyd wrote:
>
> I tried it and it doesn't work either. Typing lots of characters finally
> unjams it like you see on 1.4 hardware.
>
Can you try this? It seems to work for me on both 1.3 and 1.4 hardware
diff --git a/drivers/tty/serial/msm_serial.c b/d
On 08/05/14 17:55, Frank Rowand wrote:
> On 8/5/2014 4:53 PM, Stephen Boyd wrote:
>> On 08/05/14 12:22, Stephen Boyd wrote:
>>> I tried it and it doesn't work either. Typing lots of characters finally
>>> unjams it like you see on 1.4 hardware.
>>>
>&g
k Rowand
Fixes: f7e54d7ad743 "msm_serial: Add support for poll_{get,put}_char()"
Signed-off-by: Stephen Boyd
---
drivers/tty/serial/msm_serial.c | 22 +++---
1 file changed, 7 insertions(+), 15 deletions(-)
diff --git a/drivers/tty/serial/msm_serial.c b/drivers/tty/serial/msm_se
note that the last patch
depends on the safe switch hook that I've already sent out[1].
Stephen Boyd (3):
clk: qcom: Add support for setting rates on PLLs
clk: qcom: Add support for banked MD RCGs
clk: qcom: Add support for NSS/GMAC clocks and resets
drivers/clk/qcom/clk-
Some PLLs may require changing their rate at runtime. Add support
for these PLLs.
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/clk-pll.c | 68 +-
drivers/clk/qcom/clk-pll.h | 20 ++
2 files changed, 87 insertions(+), 1 deletion
The banked MD RCGs in global clock control have a different
register layout than the ones implemented in multimedia clock
control. Add support for these types of clocks so we can change
the rates of the UBI32 clocks.
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/clk-rcg.c | 99
like how the NSS driver
expects it. Also add the TCM clock and the NSS resets.
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/gcc-ipq806x.c | 710 ++-
include/dt-bindings/clock/qcom,gcc-ipq806x.h | 3 +
include/dt-bindings/reset/qcom,gcc-ipq806x.h | 43
On 08/05/14 19:34, Nicolas Pitre wrote:
>
>> It allows us to synchronize with another CPU that may be inside
>> gic_raise_softirq(). If the other CPU was in that function then this CPU
>> would wait until it was done sending the IPI to continue along and
>> reroute them. If the other CPU was just a
On 08/06/14 17:16, Frank Rowand wrote:
> Stephen,
>
> Can you test this patch on v 1.3 hardware? It works on my v 1.4.
>
> If you use kdmx2, the way to send a break is '~B'. The previous
> key pressed must be for the '~' escape to be recognized.
>
> Thanks!
>
> -Frank
>
>
>
> From: Frank Rowand
On 08/12/14 17:39, Nicolas Pitre wrote:
> On Tue, 12 Aug 2014, Stephen Boyd wrote:
>
>> On 08/05/14 19:34, Nicolas Pitre wrote:
>>>> It allows us to synchronize with another CPU that may be inside
>>>> gic_raise_softirq(). If the other CPU was in that function
IPI path.
Cc: Nicolas Pitre
Signed-off-by: Stephen Boyd
---
drivers/irqchip/irq-gic.c | 25 ++---
1 file changed, 22 insertions(+), 3 deletions(-)
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 7c131cf7cc13..c1dc65209899 100644
--- a/drivers/irq
On 08/12/14 17:57, Stepan Moskovchenko wrote:
> diff --git a/drivers/of/device.c b/drivers/of/device.c
> index f685e55..3e116f6 100644
> --- a/drivers/of/device.c
> +++ b/drivers/of/device.c
> @@ -54,7 +54,7 @@ int of_device_add(struct platform_device *ofdev)
>
> /* name and id have to be set
On 08/12/14 12:43, Lina Iyer wrote:
> This is version #2 of the patches for cpuidle driver and its dependencies.
>
> Changes from version #1/RFC:
>
> - Remove hotplug from the patch series. Will submit it seprately.
> - Fix SPM drivers per the review comments
> - Modify patch sequence to compile SP
On 08/12, Nicolas Pitre wrote:
> On Tue, 12 Aug 2014, Stephen Boyd wrote:
> >
> > diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
> > index 7c131cf7cc13..c1dc65209899 100644
> > --- a/drivers/irqchip/irq-gic.c
> > +++ b/drivers/irqchip/irq-gi
acquire any locks at all in the IPI path.
Cc: Nicolas Pitre
Signed-off-by: Stephen Boyd
---
drivers/irqchip/irq-gic.c | 23 +--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 7c131cf7cc13..b9e669cb1c1
On 08/13, Linus Walleij wrote:
> Can I ask a question about this ... in difference from everyone in the
> world who has APQ8070 DragonBoards I actually have the APQ8060
> DragonBoard.
>
> I have been booting this using the qcom-msm8660-surf.dts device tree
> and it seems to work reasonably well, l
On 08/11, Ivan T. Ivanov wrote:
> diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt
> b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt
> new file mode 100644
> index 000..0a64567
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp
On 08/13, Russell King - ARM Linux wrote:
> On Wed, Aug 13, 2014 at 06:57:18AM -0700, Stephen Boyd wrote:
> > Commit 1a6b69b6548c (ARM: gic: add CPU migration support,
> > 2012-04-12) introduced an acquisition of the irq_controller_lock
> > in gic_raise_softirq() which c
On 08/13, Russell King - ARM Linux wrote:
> On Wed, Aug 13, 2014 at 07:55:26AM -0700, Stephen Boyd wrote:
> > On 08/13, Russell King - ARM Linux wrote:
> > > On Wed, Aug 13, 2014 at 06:57:18AM -0700, Stephen Boyd wrote:
> > > > Commit 1a6b69b6548c (ARM: gic: add CPU m
On 08/19/14 15:15, Lina Iyer wrote:
> SPM is a hardware block that controls the peripheral logic surrounding
> the application cores (cpu/l$). When the core executes WFI instruction,
> the SPM takes over the putting the core in low power state as
> configured. The wake up for the SPM is an interrup
On 08/17/14 17:17, Nicolas Pitre wrote:
> On Sun, 17 Aug 2014, Russell King - ARM Linux wrote:
>
>> I have no problem with changing gic_raise_softirq() to use a different
>> lock, which gic_migrate_target(), and gic_set_affinity() can also use.
>> There's no need for horrid locking here, because th
On 08/17/14 18:54, Jason Cooper wrote:
>
> Stephen, is the out of tree code that triggered this bound for mainline?
>
It's bound for mainline eventually. We're actively working on enabling
more low power modes and when that happens we'll need this patch. We can
always carry this patch for now if y
ptimize
we don't take any locks at all if the BL switcher code isn't used.
Cc: Nicolas Pitre
Cc: Russell King - ARM Linux
Signed-off-by: Stephen Boyd
---
drivers/irqchip/irq-gic.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/irqchip
On 08/19/14 20:24, Lina Iyer wrote:
> On Tue, Aug 19, 2014 at 07:01:53PM -0700, Stephen Boyd wrote:
>> On 08/19/14 15:15, Lina Iyer wrote:
>>> SPM is a hardware block that controls the peripheral logic surrounding
>>> the application cores (cpu/l$). When the core execut
On 08/21/14 02:47, Russell King - ARM Linux wrote:
> What would make more sense is if this were a read-write lock, then
> gic_raise_softirq() could run concurrently on several CPUs without
> interfering with each other, yet still be safe with gic_migrate_target().
>
> I'd then argue that we wouldn'
On 08/19/14 15:15, Lina Iyer wrote:
> diff --git a/Documentation/devicetree/bindings/arm/msm/spm.txt
> b/Documentation/devicetree/bindings/arm/msm/spm.txt
> new file mode 100644
> index 000..318e024
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/msm/spm.txt
We already have a bi
On 08/25/14 17:31, Lina Iyer wrote:
> On Mon, Aug 25, 2014 at 04:40:33PM -0700, Stephen Boyd wrote:
>> On 08/19/14 15:15, Lina Iyer wrote:
>>> diff --git a/Documentation/devicetree/bindings/arm/msm/spm.txt
>>> b/Documentation/devicetree/bindings/arm/msm/spm.txt
>>
On 08/27/14 11:24, Bjorn Andersson wrote:
> On Tue, Jul 29, 2014 at 11:06 PM, Stephen Boyd wrote:
>> On 07/29, Rob Herring wrote:
> [..]
>>> You might as well do of_property_read_u32 in the below example.
>>>
>> Fair enough. The example is probably too simp
.
Cc: Kumar Gala
Cc: Andy Gross
Fixes: 24d8fba44af3 "clk: qcom: Add support for IPQ8064's global clock
controller (GCC)"
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/gcc-ipq806x.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/qcom/gcc-ipq806x.
On 08/29/14 16:41, Courtney Cavin wrote:
> On Sat, Aug 30, 2014 at 01:14:23AM +0200, Bjorn Andersson wrote:
>> From: Kumar Gala
>>
>> Add driver for Qualcomm MSM Hardware Mutex block that exists on
>> newer Qualcomm SoCs.
>>
>> Cc: Jeffrey Hugo
>> Cc: Eric Holmberg
>> Cc: Courtney Cavin
>> Sign
On 09/02/14 14:44, Mike Turquette wrote:
> Quoting Stephen Boyd (2014-08-29 12:49:26)
>> The pre-divider for the sdc clocks only has 2 bits in it, so we
>> can't possibly divide by anything larger than 4 here.
>> Furthermore, we program the value of ~(n - m) and the n
() without needing to byte-swap every word
depending on the endianess of the CPU.
Cc: Asutosh Das
Cc: Venkat Gopalakrishnan
Cc: Georgi Djakov
Fixes: 415b5a75da43 "mmc: sdhci-msm: Add platform_execute_tuning implementation"
Signed-off-by: Stephen Boyd
---
drivers/mmc/h
On 09/03, Ulf Hansson wrote:
> On 3 September 2014 01:58, Stephen Boyd wrote:
> > If we're tuning on a big-endian CPU we'll never determine we properly
> > tuned the device because we compare the data we received from the
> > controller with a table that a
() without needing to byte-swap every word
depending on the endianess of the CPU.
Cc: Asutosh Das
Cc: Venkat Gopalakrishnan
Reviewed-by: Georgi Djakov
Fixes: 415b5a75da43 "mmc: sdhci-msm: Add platform_execute_tuning implementation"
Signed-off-by: Stephen Boyd
---
drivers/mmc/h
rate() and
__clk_get_accuracy() while holding locks.
Signed-off-by: Stephen Boyd
---
drivers/clk/clk.c | 17 ++---
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index b76fa69b44cb..1feaf708aa49 100644
--- a/drivers/clk/clk.c
+++
clock locks). Introduce
a new list that contains all clocks registered in the system and
walk this list until the clock is found.
Signed-off-by: Stephen Boyd
---
drivers/clk/clk.c | 52 +
include/linux/clk-private.h | 1 +
2 files change
ted before these
patches could be applied.
This is based on clk-next as of commit 16eeaec77922 "clk: at91: fix div by zero
in USB clock driver".
Changes since v1:
* Rebased onto clk-next
Stephen Boyd (4):
clk: Recalc rate and accuracy in underscore functions if not caching
clk: Ma
is only acquiring new
locks that aren't already held.
Signed-off-by: Stephen Boyd
---
drivers/clk/clk.c | 525 +---
include/linux/clk-private.h | 3 +
2 files changed, 445 insertions(+), 83 deletions(-)
diff --git a/drivers/clk
In the near future we're going to move the prepare lock to a
per-clock ww_mutex. Use the lockless functions here for printing
the rate and accuracy so that we don't run into AA deadlocks in
the future.
Signed-off-by: Stephen Boyd
---
drivers/clk/clk.c | 8
1 file changed, 4
There are two find_freq() functions in clk-rcg.c and clk-rcg2.c
that are almost exactly the same. Consolidate them into one
function to save on some code space.
Cc: Mike Turquette
Signed-off-by: Stephen Boyd
---
I'll queue this for v3.18 if there are no objections.
drivers/clk/qcom/clk-
On 09/04/14 03:53, Ulf Hansson wrote:
> On 4 September 2014 07:06, Jaehoon Chung wrote:
>>
>> In dw-mmc.c, tuning_block values are same.
>> So I think we can move these value into generic header. how about?
> Actually, I believe these values comes from the eMMC specification?
> Shouldn't they be m
On 09/05, Jaehoon Chung wrote:
> On 09/05/2014 06:22 AM, Stephen Boyd wrote:
> > On 09/04/14 03:53, Ulf Hansson wrote:
> >> On 4 September 2014 07:06, Jaehoon Chung wrote:
> >>>
> >>> In dw-mmc.c, tuning_block values are same.
> >>> So I
c out into reusable functions
that operate on an optional table and some flags so that other
drivers can use the same logic.
Signed-off-by: Stephen Boyd
---
drivers/clk/clk-mux.c| 76 +++-
include/linux/clk-provider.h | 9 --
2 files c
s if necessary. We assume that there isn't such a thing as
minimum rate requirements.
Signed-off-by: Stephen Boyd
---
drivers/clk/clk.c | 33 +
1 file changed, 21 insertions(+), 12 deletions(-)
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index b23e2b9
Some devices don't use mmio to interact with dividers. Split out the
logic from the register read/write parts so that we can reuse the
division logic elsewhere.
Signed-off-by: Stephen Boyd
---
drivers/clk/clk-divider.c| 197 ++-
include/linu
Some clock drivers want to find the closest rate on the input of
a mux instead of a rate that's less than or equal to the desired
rate. Add a generic mux function to support this.
Signed-off-by: Stephen Boyd
---
drivers/clk/clk.c
Register a cpufreq-generic device whenever we detect that a
"qcom,krait" compatible CPU is present in DT.
Signed-off-by: Stephen Boyd
---
drivers/cpufreq/Kconfig.arm| 9 ++
drivers/cpufreq/Makefile | 1 +
drivers/cpufreq/qcom-cpufr
Add the necessary DT nodes and data so we can probe the cpufreq
driver on MSM devices with Krait CPUs.
Signed-off-by: Stephen Boyd
---
We can go faster than this, but I've limited it to the safe frequencies
until we have regulator support where we would need to increase the
voltages
Some devices don't use mmio to interact with dividers. Split out the
logic from the register read/write parts so that we can reuse the
division logic elsewhere.
Signed-off-by: Stephen Boyd
---
drivers/clk/clk-divider.c| 197 ++-
include/linu
: Stephen Boyd
---
drivers/clk/clk-mux.c| 15 +++
include/linux/clk-provider.h | 2 ++
2 files changed, 17 insertions(+)
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index 4f96ff3ba728..c0cf9db9effa 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
Describe the HFPLLs present on MSM8960 and APQ8064 devices.
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/gcc-msm8960.c | 172 +++
include/dt-bindings/clock/qcom,gcc-msm8960.h | 2 +
2 files changed, 174 insertions(+)
diff --git a/drivers/clk/qcom/gcc
On some devices (MSM8974 for example), the HFPLLs are
instantiated within the Krait processor subsystem as separate
register regions. Add a driver for these PLLs so that we can
provide HFPLL clocks for use by the system.
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/Kconfig | 8
Register a cpufreq-generic device whenever we detect that a
"qcom,krait" compatible CPU is present in DT.
Signed-off-by: Stephen Boyd
---
drivers/cpufreq/Kconfig.arm| 9 ++
drivers/cpufreq/Makefile | 1 +
drivers/cpufreq/qcom-cpufr
The Krait CPU clocks are made up of a primary mux and secondary
mux for each CPU and the L2, controlled via cp15 accessors. For
Kraits within KPSSv1 each secondary mux accepts a different aux
source, but on KPSSv2 each secondary mux accepts the same aux
source.
Signed-off-by: Stephen Boyd
: Stephen Boyd
---
drivers/clk/qcom/Kconfig | 4 ++
drivers/clk/qcom/Makefile| 1 +
drivers/clk/qcom/clk-krait.c | 166 +++
drivers/clk/qcom/clk-krait.h | 49 +
4 files changed, 220 insertions(+)
create mode 100644 drivers/clk/qcom/clk
The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. For CPUfreq
purposes probe these devices and expose a mux clock that chooses
between PXO and PLL8.
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/Kconfig| 8
drivers/clk
Describe the HFPLLs present on IPQ806X devices.
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/gcc-ipq806x.c | 83 ++
1 file changed, 83 insertions(+)
diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
index 4032e510d9aa
Add another SoC address for apq8064 and use DEBUG_UART_VIRT
instead of DEBUG_UART_BASE because the former actually exists.
Signed-off-by: Stephen Boyd
---
arch/arm/Kconfig.debug | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/Kconfig.debug b/arch/arm
HFPLLs are the main frequency source for Krait CPU clocks. Add
support for changing the rate of these PLLs.
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/Makefile| 1 +
drivers/clk/qcom/clk-hfpll.c | 253 +++
drivers/clk/qcom/clk-hfpll.h | 54
e new rate once they're
done. Add a hook that drivers can implement allowing them to
return a 'safe parent' that they can switch their parent to while
the upstream source is reprogrammed.
Signed-off-by: Stephen Boyd
---
drivers/
ge scaling (not strictly necessary)
* Document DT bindings
* Use a new efuse/eeprom API instead of hardcoding the location in the driver
* Add some thermal awareness
Stephen Boyd (15):
clk: mux: Add unregistration API
clk: mux: Split out register accessors for reuse
clk: Add __clk_mux_determi
On 09/02/14 08:45, Stanimir Varbanov wrote:
> Hi Grant,
>
> I came down to this. Could you review? Is that
> implementation closer to the suggestion made by you.
I like this patch (but I'm biased because I want it to exist). Feel free
to add my Tested-by.
> ---
> drivers/of/address.c |
d64559376f "ARM: perf: support percpu irqs for the CPU PMU"
Signed-off-by: Stephen Boyd
---
arch/arm/kernel/perf_event_cpu.c | 27 +++
1 file changed, 19 insertions(+), 8 deletions(-)
diff --git a/arch/arm/kernel/perf_event_cpu.c b/arch/arm/kernel/perf_event_cpu.
Adding Mark Brown who finished off introducing IORESOURCE_REG.
On 09/08/14 07:52, Grant Likely wrote:
> On Tue, 2 Sep 2014 18:45:00 +0300, Stanimir Varbanov
> wrote:
>> +
>> unsigned long __weak pci_address_to_pio(phys_addr_t address)
>> {
>> if (address > IO_SPACE_LIMIT)
>> @@ -665,6 +6
On 09/08/14 16:34, Rafael J. Wysocki wrote:
> On Thursday, August 28, 2014 11:22:31 AM Viresh Kumar wrote:
>> The naming convention of this driver was always under the scanner, people
>> complained that it should have a more generic name than cpu0, as it manages
>> all
>> CPUs that are sharing clo
On 09/08/14 16:52, Rafael J. Wysocki wrote:
> So more bikeshedding. :-)
>
> Isn't "generic" somewhat too broad? Surely it doesn't cover x86. And does
> it actually cover anything without clocks/regulators?
>
I thought when you bikeshed you have to come up with a different color ;-)
Perhaps "cpu
On 09/07/14 21:46, Viresh Kumar wrote:
> On 6 September 2014 04:17, Stephen Boyd wrote:
>
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 and
>> + * only version 2 as publis
On 09/09/14 04:39, Will Deacon wrote:
> It's interesting that arm64 isn't affected by this problem, since we don't
> update the active_irqs mask for PPIs there and consequently just pass the
> irq instead of the cpu_pmu. I can't see why we actually need to update the
> active_irqs mask for arch/arm
On 09/10/14 02:53, Arnd Bergmann wrote:
>
> Most of us will be at LCU next week, so I'd suggest we solve this
> problem using the 'lock everyone into one room without beer until
> we come up with a working approach' method.
>
I'll be at connect Tuesday to mid-Thursday. I'd like to be included if
s
On 09/10/14 11:21, Will Deacon wrote:
> On Tue, Sep 09, 2014 at 06:54:45PM +0100, Stephen Boyd wrote:
>
>> Here's the interdiff. Is there a reason arm64 casts data to an unsigned
>> int pointer when what's passed is an int pointer?
> There has to be a cast to s
the irq
directly to the enable/disable functions to clean all this up.
This should be slightly more efficient and also fix the
scheduling while atomic bug.
Reported-by: Rob Clark
Fixes: bbd64559376f "ARM: perf: support percpu irqs for the CPU PMU"
Acked-by: Will Deacon
Signed-off-by: Ste
On 07/10/14 07:26, Maxime Ripard wrote:
>
> I guess that the kind of things we could discuss after posting these
> patches, but yep, it looks reasonnable.
>
> I'll try to get things a bit cleaner, and post them in the next days.
>
I never saw anything. Did you do any cleaning/posting? I'm going to
Add support for DT based early console on platforms with the msm
serial hardware.
Cc: Rob Herring
Signed-off-by: Stephen Boyd
---
drivers/tty/serial/Kconfig | 1 +
drivers/tty/serial/msm_serial.c | 72 ++---
2 files changed, 61 insertions(+), 12
101 - 200 of 2121 matches
Mail list logo
