On Fri, May 30, 2014 at 3:30 AM, Stephen Boyd wrote:
> Hm... that doesn't sound right. Please see this thread on lkml[1], and
> also this video from Ben H.[2]
But Benji is talking about the *PCI BUS*, and this is raw register
access. He just says that "This is how a BE CPU is normally
wired to a
On 05/29/14 00:43, Linus Walleij wrote:
> On Wed, May 28, 2014 at 3:57 PM, Srinivas Kandagatla
> wrote:
>
>>> This doesn't look endianness agnostic. Shouldn't we use ioread32_rep()
>>> to read this fifo?
>> Is'nt readl endianess aware?
> At least once a year read through arch/arm/include/asm/io.h
On Wed, May 28, 2014 at 3:57 PM, Srinivas Kandagatla
wrote:
>> This doesn't look endianness agnostic. Shouldn't we use ioread32_rep()
>> to read this fifo?
>
> Is'nt readl endianess aware?
At least once a year read through arch/arm/include/asm/io.h
static inline u32 __raw_readl(const volatile v
Sorry Stephen for late reply,
Some reason this mail was filtered in other folders.
On 24/05/14 00:28, Stephen Boyd wrote:
On 05/23/14 05:53, srinivas.kandaga...@linaro.org wrote:
@@ -1022,6 +1025,40 @@ mmci_cmd_irq(struct mmci_host *host, struct mmc_command
*cmd,
}
}
+static int mmc
On 28/05/14 09:08, Linus Walleij wrote:
On Fri, May 23, 2014 at 2:53 PM, wrote:
+ if (unlikely(bytes)) {
+ unsigned char buf[4];
(...)
Please think twice about this.
http://lwn.net/Articles/70473/
http://lwn.net/Articles/420019/
http://lwn.net/Articles/182369/
Tha
On Fri, May 23, 2014 at 2:53 PM, wrote:
> + if (unlikely(bytes)) {
> + unsigned char buf[4];
(...)
Please think twice about this.
http://lwn.net/Articles/70473/
http://lwn.net/Articles/420019/
http://lwn.net/Articles/182369/
Yours,
Linus Walleij
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On 26/05/14 15:34, Ulf Hansson wrote:
This is hot path.
As I suggested for the readl and writel wrapper functions, I think it
would be better to use a function pointer in the struct mmci host,
which you set up in the probe phase. That means the variant data don't
need to be checked each an eve
On 23 May 2014 14:53, wrote:
> From: Srinivas Kandagatla
>
> MCIFIFOCNT register behaviour on Qcom chips is very different than the other
> pl180 integrations. MCIFIFOCNT register contains the number of
> words that are still waiting to be transferred through the FIFO. It keeps
> decrementing on
On 05/23/14 05:53, srinivas.kandaga...@linaro.org wrote:
> @@ -1022,6 +1025,40 @@ mmci_cmd_irq(struct mmci_host *host, struct
> mmc_command *cmd,
> }
> }
>
> +static int mmci_qcom_pio_read(struct mmci_host *host, char *buffer,
> + unsigned int remain)
> +{
> + u32
From: Srinivas Kandagatla
MCIFIFOCNT register behaviour on Qcom chips is very different than the other
pl180 integrations. MCIFIFOCNT register contains the number of
words that are still waiting to be transferred through the FIFO. It keeps
decrementing once the host CPU reads the MCIFIFO. With th
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