Re: [PATCH v4 1/5] PCI: designware: add memory barrier after enabling region

2015-12-22 Thread Jingoo Han
On Friday, December 11, 2015 2:49 PM, Jisheng Zhang wrote: > > On Fri, 11 Dec 2015 09:35:10 +0530 Pratyush Anand wrote: > > > On Wed, Dec 9, 2015 at 3:53 PM, Russell King - ARM Linux wrote: > > > > [...] > > > > >> > > dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2); > > >> > > +

Re: [PATCH v4 1/5] PCI: designware: add memory barrier after enabling region

2015-12-17 Thread Stanimir Varbanov
On 12/11/2015 06:05 AM, Pratyush Anand wrote: > On Wed, Dec 9, 2015 at 3:53 PM, Russell King - ARM Linux > wrote: > > [...] > > dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2); > + /* > + * ensure that the ATU enable has been happaned

Re: [PATCH v4 1/5] PCI: designware: add memory barrier after enabling region

2015-12-17 Thread Pratyush Anand
On Thu, Dec 17, 2015 at 9:15 PM, Stanimir Varbanov wrote: > > On 12/11/2015 06:05 AM, Pratyush Anand wrote: > > On Wed, Dec 9, 2015 at 3:53 PM, Russell King - ARM Linux > > wrote: > > > > [...] > > > > dw_pcie_writel_rc(pp,

Re: [PATCH v4 1/5] PCI: designware: add memory barrier after enabling region

2015-12-10 Thread Pratyush Anand
On Wed, Dec 9, 2015 at 3:53 PM, Russell King - ARM Linux wrote: [...] >> > > dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2); >> > > + /* >> > > + * ensure that the ATU enable has been happaned before accessing >> > > + * pci configuration/io

Re: [PATCH v4 1/5] PCI: designware: add memory barrier after enabling region

2015-12-10 Thread Jisheng Zhang
On Fri, 11 Dec 2015 09:35:10 +0530 Pratyush Anand wrote: > On Wed, Dec 9, 2015 at 3:53 PM, Russell King - ARM Linux wrote: > > [...] > > >> > > dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2); > >> > > + /* > >> > > + * ensure that the ATU enable has been happaned before

Re: [PATCH v4 1/5] PCI: designware: add memory barrier after enabling region

2015-12-09 Thread Russell King - ARM Linux
On Wed, Dec 09, 2015 at 10:10:05AM +0530, Pratyush Anand wrote: > On Tue, Dec 8, 2015 at 2:31 PM, Stanimir Varbanov > wrote: > > > > On 12/03/2015 03:35 PM, Stanimir Varbanov wrote: > > > Add 'write memory' barrier after enable region in PCIE_ATU_CR2 > > > register.

Re: [PATCH v4 1/5] PCI: designware: add memory barrier after enabling region

2015-12-09 Thread Stanimir Varbanov
On 12/09/2015 11:52 AM, Arnd Bergmann wrote: > On Wednesday 09 December 2015 10:10:05 Pratyush Anand wrote: >> On Tue, Dec 8, 2015 at 2:31 PM, Stanimir Varbanov Signed-off-by: Stanimir Varbanov --- drivers/pci/host/pcie-designware.c |5 +

Re: [PATCH v4 1/5] PCI: designware: add memory barrier after enabling region

2015-12-09 Thread Arnd Bergmann
On Wednesday 09 December 2015 10:10:05 Pratyush Anand wrote: > On Tue, Dec 8, 2015 at 2:31 PM, Stanimir Varbanov > > > Signed-off-by: Stanimir Varbanov > > > --- > > > drivers/pci/host/pcie-designware.c |5 + > > > 1 file changed, 5 insertions(+) > > > > > >

Re: [PATCH v4 1/5] PCI: designware: add memory barrier after enabling region

2015-12-08 Thread Stanimir Varbanov
On 12/03/2015 03:35 PM, Stanimir Varbanov wrote: > Add 'write memory' barrier after enable region in PCIE_ATU_CR2 > register. The barrier is needed to ensure that the region enable > request has been reached it's destination at time when we > read/write to PCI configuration space. > > Without

Re: [PATCH v4 1/5] PCI: designware: add memory barrier after enabling region

2015-12-08 Thread Pratyush Anand
On Tue, Dec 8, 2015 at 2:31 PM, Stanimir Varbanov wrote: > > On 12/03/2015 03:35 PM, Stanimir Varbanov wrote: > > Add 'write memory' barrier after enable region in PCIE_ATU_CR2 > > register. The barrier is needed to ensure that the region enable > > request has been

[PATCH v4 1/5] PCI: designware: add memory barrier after enabling region

2015-12-03 Thread Stanimir Varbanov
Add 'write memory' barrier after enable region in PCIE_ATU_CR2 register. The barrier is needed to ensure that the region enable request has been reached it's destination at time when we read/write to PCI configuration space. Without this barrier PCI device enumeration during kernel boot is not