Hi,
On Fri, Apr 04, 2014 at 03:18:11PM -0700, Tim Bird wrote:
Select the secondary PHY using the TCSR register, if phy-num=1
in the DTS (or phy_number is set in the platform data). The
SOC has 2 PHYs which can be used with the OTG port, and this
code allows configuring the correct one.
On Mon, Apr 21, 2014 at 12:30:42AM -0500, Andy Gross wrote:
The GSBI (General Serial Bus Interface) driver controls the overarching
configuration of the shared serial bus infrastructure on APQ8064, IPQ8064, and
earlier QCOM processors. The GSBI supports UART, I2C, SPI, and UIM
functionality
On Mon, Apr 21, 2014 at 11:54:00AM -0500, Josh Cartwright wrote:
snip
+
+struct gsbi_dev {
+ struct device *dev;
+ void __iomem*base;
You don't really need these.
Old habits die hard. I'll remove.
snip
+ if (of_property_read_u32(node, qcom,mode, mode)) {
+
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch series adds Qualcomm SD Card Controller support in pl180 mmci
driver. QCom SDCC is basically a pl180, but bit more customized, some of the
register layouts and offsets are different to the ones mentioned in pl180
datasheet. The
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
Instance of this IP on Qualcomm's SOCs has bit different layout for datactrl
register. Bit postion datactrl[16:4] hold the true block size instead of power
of 2.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
---
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds write delay parameter required after each write to controller
registers on some of the SOCs like Qualcomm ones. The delay parameter will
provide information on how many clock cycle delay required after each write.
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds wrappers for readl/writel functions used in the driver. The
reason for this wrappers is to accommodate SOCs like Qualcomm which has
requirement for delaying the write for few cycles when writing to its SD Card
Controller
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
MCICLK going to card bus is directly driven by the clock controller, so the
driver has to set the required rates depending on the state of the card. This
bit of support is very much similar to bypass mode but there is no such thing
called
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
MCIFIFOCNT register behaviour on Qcom chips is very different than the other
pl180 integrations. MCIFIFOCNT register contains the number of
words that are still waiting to be transferred through the FIFO. It keeps
decrementing once the host
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
MCICLK register layout is bit different to the standard pl180 register layout.
Qcom SDCC controller some setup in MCICLK register to get it going. So this
patch adds new setup and makes it specific to Qcom hw designer.
Signed-off-by:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
Some bits which control Command Path State Machine (CPSM) are new in Qcom
integration, so this patch adds support to those bits.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
---
drivers/mmc/host/mmci.c |4
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch replaces a constant used in calculating timeout with a proper
macro. This is make code more readable.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
---
drivers/mmc/host/mmci.c |2 +-
1 file changed, 1
On 04/21/14 14:49, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
MCICLK going to card bus is directly driven by the clock controller, so the
driver has to set the required rates depending on the state of the card. This
bit of support is very
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