Re: [PATCH v5 02/13] mmc: mmci: convert register bits to use BIT() macro.

2014-06-02 Thread Srinivas Kandagatla
Thanks Russell, On 31/05/14 13:35, Russell King - ARM Linux wrote: because allegedly it makes it more readable. I don't see much benefit to this patch. Ok, I will drop this patch in next version. thanks, srini -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the

Re: [PATCH 0/3] Qualcomm Resource Power Manager driver

2014-06-02 Thread Stanimir Varbanov
Hi Bjorn, Thanks for the patches. snip Lately I've been working on rpm, rpm-smd, smem, smd, smsm, smp2p patches for mainline. It could be argued that smd is a bus and should go in drivers/bus, but for the rest I fear that we just created drivers/soc/qcom as another dumping ground for

[PATCH v6 00/12] Qualcomm SD Card Controller support

2014-06-02 Thread srinivas . kandagatla
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org Thankyou Linus W, Ulf H, Russell K and everyone for reviewing RFC to v5 patches. This patch series adds Qualcomm SD Card Controller support in pl180 mmci driver. QCom SDCC is basically a pl180, but bit more customized, some of the register

[PATCH v6 01/12] mmc: mmci: use NSEC_PER_SEC macro

2014-06-02 Thread srinivas . kandagatla
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org This patch replaces a constant used in calculating timeout with a proper macro. This is make code more readable. Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org Reviewed-by: Linus Walleij linus.wall...@linaro.org ---

[PATCH v6 09/12] mmc: mmci: add f_max to variant structure

2014-06-02 Thread srinivas . kandagatla
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org Some of the controller have maximum supported frequency, This patch adds support in variant data structure to specify such restrictions. This gives more flexibility in calculating the f_max before passing it to mmc-core. Signed-off-by:

[PATCH v6 10/12] mmc: mmci: add explicit clk control

2014-06-02 Thread srinivas . kandagatla
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org On Controllers like Qcom SD card controller where cclk is mclk and mclk should be directly controlled by the driver. This patch adds support to control mclk directly in the driver, and also adds explicit_mclk_control flag in variant

[PATCH v6 12/12] mmc: mmci: Add Qualcomm Id to amba id table

2014-06-02 Thread srinivas . kandagatla
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org This patch adds a fake Qualcomm ID 0x00051180 to the amba_ids, as Qualcomm SDCC controller is pl180, but amba id registers read 0x0's. The plan is to remove SDCC driver totally and use mmci as the main SD controller driver for Qualcomm

[PATCH v6 11/12] mmc: mmci: Add Qcom specific rx_fifocnt logic.

2014-06-02 Thread srinivas . kandagatla
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org MCIFIFOCNT register behaviour on Qcom chips is very different than the other pl180 integrations. MCIFIFOCNT register contains the number of words that are still waiting to be transferred through the FIFO. It keeps decrementing once the host

[PATCH v6 03/12] mmc: mmci: Add enough delay between writes to CMD register.

2014-06-02 Thread srinivas . kandagatla
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org On Qcom SD Card controller POWER, CLKCTRL, DATACTRL and COMMAND registers should be updated in MCLK domain, and writes to these registers must be separated by three MCLK cycles. This resitriction is not applicable for other registers. Any

[PATCH v6 05/12] mmc: mmci: add ddrmode mask to variant data

2014-06-02 Thread srinivas . kandagatla
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org This patch adds ddrmode mask to variant structure giving more flexibility to the driver to support more SOCs which have different datactrl register layout. Without this patch datactrl register is updated with incorrect ddrmode mask,

[PATCH v6 04/12] mmc: mmci: Add Qcom datactrl register variant

2014-06-02 Thread srinivas . kandagatla
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org Instance of this IP on Qualcomm's SOCs has bit different layout for datactrl register. Bit position datactrl[16:4] hold the true block size instead of power of 2. Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org

[PATCH v6 06/12] mmc: mmci: add 8bit bus support in variant data

2014-06-02 Thread srinivas . kandagatla
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org This patch adds 8bit bus enable to variant structure giving more flexibility to the driver to support more SOCs which have different clock register layout. Without this patch other new SOCs like Qcom will have to add more code to special

[PATCH v6 07/12] mmc: mmci: add edge support to data and command out in variant data.

2014-06-02 Thread srinivas . kandagatla
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org This patch adds edge support for data and command out to variant structure giving more flexibility to the driver to support more SOCs which have different clock register layout. Without this patch other new SOCs like Qcom will have to add

[PATCH v6 08/12] mmc: mmci: Add support to data commands via variant structure.

2014-06-02 Thread srinivas . kandagatla
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org On some SOCs like Qcom there are explicit bits in the command register to specify if its a data transfer command or not. So this patch adds support to such bits in variant data, giving more flexibility to the driver. Signed-off-by:

[PATCH v6 02/12] mmc: mmci: Add Qualcomm specific register defines.

2014-06-02 Thread srinivas . kandagatla
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org This patch adds a Qualcomm SD Card controller specific register variations to header file. Qualcomm SDCC controller is pl180, with slight changes in the register layout from standard pl180 register set. Signed-off-by: Srinivas Kandagatla

Re: [PATCH 0/3] Qualcomm Resource Power Manager driver

2014-06-02 Thread Mark Brown
On Mon, Jun 02, 2014 at 11:15:24AM +0300, Stanimir Varbanov wrote: Lately I've been working on rpm, rpm-smd, smem, smd, smsm, smp2p patches for mainline. It could be argued that smd is a bus and should go in drivers/bus, but for the rest I fear that we just created drivers/soc/qcom as

Re: [PATCH] tty: serial: msm_serial.c: Cleaning up uninitialized variables

2014-06-02 Thread Daniel Thompson
On 01/06/14 14:38, Rickard Strandqvist wrote: There is a risk that the variable will be used without being initialized. This was largely found by using a static code analysis program called cppcheck. Signed-off-by: Rickard Strandqvist rickard_strandqv...@spectrumdigital.se ---

Re: [PATCH 1/2] pci: Add IORESOURCE_BIT entry for PCIe ECAM resources.

2014-06-02 Thread Grant Likely
On Sat, 31 May 2014 20:41:04 +0200, Arnd Bergmann a...@arndb.de wrote: On Saturday 31 May 2014 01:36:40 Liviu Dudau wrote: We would like to be able to describe PCIe ECAM resources as IORESOURCE_MEM blocks while distinguish them from standard memory resources. Add an IORESOURCE_BIT entry for

Re: [PATCH 1/2] pci: Add IORESOURCE_BIT entry for PCIe ECAM resources.

2014-06-02 Thread Kumar Gala
On Jun 2, 2014, at 10:09 AM, Grant Likely grant.lik...@linaro.org wrote: On Sat, 31 May 2014 20:41:04 +0200, Arnd Bergmann a...@arndb.de wrote: On Saturday 31 May 2014 01:36:40 Liviu Dudau wrote: We would like to be able to describe PCIe ECAM resources as IORESOURCE_MEM blocks while

Re: [PATCH 1/2] pci: Add IORESOURCE_BIT entry for PCIe ECAM resources.

2014-06-02 Thread Grant Likely
On Mon, 2 Jun 2014 10:40:30 -0500, Kumar Gala ga...@codeaurora.org wrote: On Jun 2, 2014, at 10:09 AM, Grant Likely grant.lik...@linaro.org wrote: On Sat, 31 May 2014 20:41:04 +0200, Arnd Bergmann a...@arndb.de wrote: On Saturday 31 May 2014 01:36:40 Liviu Dudau wrote: We would like to

Re: [PATCH 1/2] pci: Add IORESOURCE_BIT entry for PCIe ECAM resources.

2014-06-02 Thread Kumar Gala
On Jun 2, 2014, at 11:23 AM, Grant Likely grant.lik...@linaro.org wrote: On Mon, 2 Jun 2014 10:40:30 -0500, Kumar Gala ga...@codeaurora.org wrote: On Jun 2, 2014, at 10:09 AM, Grant Likely grant.lik...@linaro.org wrote: On Sat, 31 May 2014 20:41:04 +0200, Arnd Bergmann a...@arndb.de

Re: [PATCH 1/2] pci: Add IORESOURCE_BIT entry for PCIe ECAM resources.

2014-06-02 Thread Arnd Bergmann
On Monday 02 June 2014 13:09:08 Kumar Gala wrote: However, what do we do with the 2 cases that exist in upstream that are using ranges for cfg space? Ignore them in the core code? Make the specific host controller handle them I would think. I just meant, should we ‘break’ their DTs

Re: [PATCH v2 2/4] clk: qcom: Add APQ8084 Global Clock Controller support

2014-06-02 Thread Stephen Boyd
On 05/31, Georgi Djakov wrote: + +static const struct qcom_reset_map gcc_apq8084_resets[] = { + [GCC_VENUS0_BCR] = { 0x1020 }, + [GCC_VPU_BCR] = { 0x1400 }, + [GCC_MDSS_BCR] = { 0x2300 }, + [GCC_AVSYNC_BCR] = { 0x2400 }, + [GCC_OXILI_BCR] = { 0x4020 }, +

Re: [PATCH v2 4/4] ARM: dts: qcom: Add APQ8084 serial port DT node

2014-06-02 Thread Stephen Boyd
On 05/31, Georgi Djakov wrote: Add the necessary DT node to probe the serial driver on APQ8084 platforms. Signed-off-by: Georgi Djakov gdja...@mm-sol.com Reviewed-by: Stephen Boyd sb...@codeaurora.org -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux

Re: [PATCH v2 1/4] clk: qcom: Add APQ8084 Global Clock Controller documentation

2014-06-02 Thread Stephen Boyd
On 05/31, Georgi Djakov wrote: Add the compatible string for the APQ8084 global clock controller to the clock binding documentation. Signed-off-by: Georgi Djakov gdja...@mm-sol.com Reviewed-by: Stephen Boyd sb...@codeaurora.org -- Qualcomm Innovation Center, Inc. is a member of Code Aurora

Re: [PATCH v2 3/4] ARM: dts: qcom: Add APQ8084 Global Clock Controller DT node

2014-06-02 Thread Stephen Boyd
On 05/31, Georgi Djakov wrote: This patch adds the necessary node to probe the global clock controller on APQ8084 platforms. Signed-off-by: Georgi Djakov gdja...@mm-sol.com Reviewed-by: Stephen Boyd sb...@codeaurora.org -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,

Re: [PATCH v2 2/4] clk: qcom: Add APQ8084 Global Clock Controller support

2014-06-02 Thread Georgi Djakov
On 02.06.14, 22:36, Stephen Boyd wrote: On 05/31, Georgi Djakov wrote: + +static const struct qcom_reset_map gcc_apq8084_resets[] = { +[GCC_VENUS0_BCR] = { 0x1020 }, +[GCC_VPU_BCR] = { 0x1400 }, +[GCC_MDSS_BCR] = { 0x2300 }, +[GCC_AVSYNC_BCR] = { 0x2400 }, +

Re: [PATCH 1/2] pci: Add IORESOURCE_BIT entry for PCIe ECAM resources.

2014-06-02 Thread Kumar Gala
On Jun 2, 2014, at 2:15 PM, Arnd Bergmann a...@arndb.de wrote: On Monday 02 June 2014 13:09:08 Kumar Gala wrote: However, what do we do with the 2 cases that exist in upstream that are using ranges for cfg space? Ignore them in the core code? Make the specific host controller handle them

Re: [PATCH 1/2] pci: Add IORESOURCE_BIT entry for PCIe ECAM resources.

2014-06-02 Thread Arnd Bergmann
On Monday 02 June 2014 15:43:02 Kumar Gala wrote: Its imx6 and exynos, havent looked to see if dw-pcie is handling the parsing or not for them. Ok, so they are both dw-pcie variants. Arnd -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a

Re: [PATCH] tty: serial: msm_serial.c: Cleaning up uninitialized variables

2014-06-02 Thread dwalker
On Sun, Jun 01, 2014 at 03:38:24PM +0200, Rickard Strandqvist wrote: There is a risk that the variable will be used without being initialized. This was largely found by using a static code analysis program called cppcheck. Signed-off-by: Rickard Strandqvist