Re: [PATCH v5 3/3] dt/bindings: qcom_nandc: Add DT bindings

Hi Archit, On Tue, 5 Jan 2016 10:55:01 +0530 Archit Taneja wrote: > Add DT bindings document for the Qualcomm NAND controller driver. > > Cc: devicet...@vger.kernel.org > Cc: Rob Herring > Signed-off-by: Archit Taneja > --- >

Re: [PATCH v5 3/3] dt/bindings: qcom_nandc: Add DT bindings

On Tue, Jan 05, 2016 at 10:55:01AM +0530, Archit Taneja wrote: > Add DT bindings document for the Qualcomm NAND controller driver. > > Cc: devicet...@vger.kernel.org > Cc: Rob Herring > Signed-off-by: Archit Taneja > --- > v5: > - Make changes to

Re: [PATCH v5 1/3] mtd: nand: don't select chip in nand_chip's block_bad op

On Tue, 5 Jan 2016 10:54:59 +0530 Archit Taneja wrote: > One of the arguments passed to struct nand_chip's block_bad op is > 'getchip', which, if true, is supposed to get and select the nand device, > and later unselect and release the device. > > This op is intended to

Re: [PATCH v5 3/3] dt/bindings: qcom_nandc: Add DT bindings

On Wed, 6 Jan 2016 09:14:44 -0600 Rob Herring wrote: > On Tue, Jan 05, 2016 at 10:55:01AM +0530, Archit Taneja wrote: > > Add DT bindings document for the Qualcomm NAND controller driver. > > > > Cc: devicet...@vger.kernel.org > > Cc: Rob Herring > >

Re: [PATCH v5 1/5] PCI: designware: ensure ATU is enabled before IO/conf space accesses

[+cc Jisheng] On Fri, Dec 18, 2015 at 02:38:55PM +0200, Stanimir Varbanov wrote: > There is no guarantees that enabling ATU will hit the hardware > immediately, and subsequent accesses to configuration / IO spaces > are reliable. So fixing this by read back PCIE_ATU_CR2 register > just after

Re: [PATCH v5 3/3] dt/bindings: qcom_nandc: Add DT bindings

On Wed, Jan 6, 2016 at 9:37 AM, Boris Brezillon wrote: > On Wed, 6 Jan 2016 09:14:44 -0600 > Rob Herring wrote: > >> On Tue, Jan 05, 2016 at 10:55:01AM +0530, Archit Taneja wrote: >> > Add DT bindings document for the Qualcomm NAND controller

Re: [PATCH v5 2/3] mtd: nand: Qualcomm NAND controller driver

Hi Archit, On Tue, 5 Jan 2016 10:55:00 +0530 Archit Taneja wrote: > The Qualcomm NAND controller is found in SoCs like IPQ806x, MSM7xx, > MDM9x15 series. > > It exists as a sub block inside the IPs EBI2 (External Bus Interface 2) > and QPIC (Qualcomm Parallel Interface

Re: [PATCH 1/3] driver-core: platform: Add platform_irq_count()

On Wed, Jan 6, 2016 at 7:12 PM, Stephen Boyd wrote: > A recent patch added calls to of_irq_count() in the qcom pinctrl > drivers and that caused module build failures because > of_irq_count() is not an exported symbol. We shouldn't export > of_irq_count() to modules because

Re: [PATCH 1/3] driver-core: platform: Add platform_irq_count()

On Wed, Jan 06, 2016 at 05:12:47PM -0800, Stephen Boyd wrote: > A recent patch added calls to of_irq_count() in the qcom pinctrl > drivers and that caused module build failures because > of_irq_count() is not an exported symbol. We shouldn't export > of_irq_count() to modules because it's an

Re: [PATCH] mfd: qcom-spmi-pmic: Don't access non-existing registers

On 11/17/15 16:06, Stephen Boyd wrote: > From: "Ivan T. Ivanov" > > Revision ID registers are available only on devices with > Slave IDs that are even, so don't make access to unavailable > registers. > > Signed-off-by: Ivan T. Ivanov >

Re: [PATCH v5 1/3] mtd: nand: don't select chip in nand_chip's block_bad op

On 01/06/2016 09:35 PM, Boris Brezillon wrote: On Tue, 5 Jan 2016 10:54:59 +0530 Archit Taneja wrote: One of the arguments passed to struct nand_chip's block_bad op is 'getchip', which, if true, is supposed to get and select the nand device, and later unselect and

Re: [PATCH 2/3] pinctrl: qcom: Use platform_irq_count() instead of of_irq_count()

On 01/06/16 17:19, Bjorn Andersson wrote: > On Wed, Jan 6, 2016 at 5:12 PM, Stephen Boyd wrote: >> of_irq_count() is not an exported symbol (and it shouldn't be >> used by platform drivers anyway) so use platform_irq_count() >> instead. This allows us to make the qcom

[PATCH v2 2/3] pinctrl: qcom: Use platform_irq_count() instead of of_irq_count()

of_irq_count() is not an exported symbol (and it shouldn't be used by platform drivers anyway) so use platform_irq_count() instead. This allows us to make the qcom pinctrl drivers modular again. Cc: Rob Herring Cc: Andy Gross Cc: Bjorn Andersson

Re: [PATCH v2 1/5] devicetree: bindings: Document qcom board compatible format

On 11/23/15 16:47, Stephen Boyd wrote: > On 11/22, Rob Herring wrote: >> >> Much more reasonable now. I do find the '/' in it a bit strange though. > I can remove the backslash if you like. Is a dash more preferred? > >> Acked-by: Rob Herring >> > and if so can I keep the ack?

[PATCH 1/3] driver-core: platform: Add platform_irq_count()

A recent patch added calls to of_irq_count() in the qcom pinctrl drivers and that caused module build failures because of_irq_count() is not an exported symbol. We shouldn't export of_irq_count() to modules because it's an internal OF API that shouldn't be used by drivers. Platform drivers should

[PATCH 2/3] pinctrl: qcom: Use platform_irq_count() instead of of_irq_count()

of_irq_count() is not an exported symbol (and it shouldn't be used by platform drivers anyway) so use platform_irq_count() instead. This allows us to make the qcom pinctrl drivers modular again. Cc: Rob Herring Cc: Andy Gross Signed-off-by: Stephen

Re: [PATCH 2/3] pinctrl: qcom: Use platform_irq_count() instead of of_irq_count()

On Wed, Jan 6, 2016 at 5:12 PM, Stephen Boyd wrote: > of_irq_count() is not an exported symbol (and it shouldn't be > used by platform drivers anyway) so use platform_irq_count() > instead. This allows us to make the qcom pinctrl drivers modular > again. > [..] > diff --git

[PATCH] arm: dts: qcom: Add more board clocks

These clocks are fixed rate board sources that should be in DT. Add them. Cc: Georgi Djakov Signed-off-by: Stephen Boyd --- It seems that I never sent out the updated version of this patch to cover all the SoCs we have. This is on top of

Re: [PATCH v5 1/5] PCI: designware: ensure ATU is enabled before IO/conf space accesses

Dear Bjorn, On Wed, 6 Jan 2016 12:20:03 -0600 Bjorn Helgaas wrote: > [+cc Jisheng] > > On Fri, Dec 18, 2015 at 02:38:55PM +0200, Stanimir Varbanov wrote: > > There is no guarantees that enabling ATU will hit the hardware > > immediately, and subsequent accesses to configuration / IO spaces > >

Re: [PATCH 1/5] [v2] usb: host: ehci-msm: Allow LS devices to work

Timur Tabi wrote: From: Jack Pham Disable the silicon quirk which is normally enabled for HSIC host mode. This would otherwise prevent low speed devices from enumerating properly. Signed-off-by: Jack Pham Signed-off-by: Timur Tabi