will only support slave DMA operations
between system memory and peripherals.
Andy Gross (2):
dmaengine: add msm bam dma driver
dmaengine: msm_bam_dma: Add device tree binding
.../devicetree/bindings/dma/msm_bam_dma.txt| 49 ++
drivers/dma/Kconfig
the peripheral and system memory (System mode) or
between two peripherals (BAM2BAM).
The initial release of this driver only supports slave transfers between
peripherals and system memory.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/dma/Kconfig|9 +
drivers/dma/Makefile
Add device tree probe support for the MSM BAM DMA driver.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
.../devicetree/bindings/dma/msm_bam_dma.txt| 49
1 file changed, 49 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/msm_bam_dma.txt
On Tue, Oct 29, 2013 at 10:56:03AM -0700, Stephen Boyd wrote:
On 10/25, Andy Gross wrote:
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index f238cfd..a71b415 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -364,4 +364,13 @@ config DMATEST
Simple DMA test
On Thu, Oct 31, 2013 at 04:46:21PM -0500, Andy Gross wrote:
On Thu, Oct 31, 2013 at 10:29:48PM +0530, Vinod Koul wrote:
On Fri, Oct 25, 2013 at 03:24:02PM -0500, Andy Gross wrote:
This should be sent to dmaeng...@vger.kernel.org
I'll add the list when I send the second iteration
On Wed, Nov 13, 2013 at 06:48:12PM +0530, Vinod Koul wrote:
On Thu, Nov 07, 2013 at 05:03:17PM -0600, Andy Gross wrote:
On Thu, Oct 31, 2013 at 04:46:21PM -0500, Andy Gross wrote:
On Thu, Oct 31, 2013 at 10:29:48PM +0530, Vinod Koul wrote:
On Fri, Oct 25, 2013 at 03:24:02PM -0500, Andy
- Removed proprietary slave config. Removed associated include file.
- Renamed files to reflect vendor name instead of specific device
- Converted to use (readl|writel)_relaxed w/ appropriate barriers
- Removed unions in favor of standard types.
Andy Gross (2):
dmaengine: add
Add device tree binding support for the QCOM BAM DMA driver.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
.../devicetree/bindings/dma/qcom_bam_dma.txt | 52 ++
1 file changed, 52 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma
the peripheral and system memory (System mode), or
between two peripherals (BAM2BAM).
The initial release of this driver only supports slave transfers between
peripherals and system memory.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/dma/Kconfig| 9 +
drivers/dma/Makefile
On Fri, Jan 17, 2014 at 11:49:27PM +0100, Arnd Bergmann wrote:
On Friday 10 January 2014, Andy Gross wrote:
+static bool bam_dma_filter(struct dma_chan *chan, void *data)
+{
+ struct bam_filter_args *args = data;
+ struct bam_chan *bchan = to_bam_chan(chan);
+
+ if (args-dev
On Tue, Jan 14, 2014 at 11:43:48AM -0800, Stephen Boyd wrote:
(Mostly nitpicks)
On 01/10, Andy Gross wrote:
Add the DMA engine driver for the QCOM Bus Access Manager (BAM) DMA
controller
found in the MSM 8x74 platforms.
Each BAM DMA device is associated with a specific on-chip
On Mon, Jan 13, 2014 at 10:31:01AM +, Shevchenko, Andriy wrote:
On Fri, 2014-01-10 at 13:07 -0600, Andy Gross wrote:
Add the DMA engine driver for the QCOM Bus Access Manager (BAM) DMA
controller
found in the MSM 8x74 platforms.
Each BAM DMA device is associated with a specific
On Tue, Jan 21, 2014 at 09:03:43AM +0100, Arnd Bergmann wrote:
On Monday 20 January 2014 16:52:45 Andy Gross wrote:
+#ifdef CONFIG_OF
+static const struct of_device_id bam_of_match[] = {
+ { .compatible = qcom,bam-v1.4.0, },
+ { .compatible = qcom,bam-v1.4.1
On Thu, Jan 23, 2014 at 02:17:19PM -0600, Kumar Gala wrote:
[]
Thanks for the clarification. I think I'll probably do:
ARCH_MSM_DT || (COMPILE_TEST ARM)
Didn?t you need it to be:
ARCH_MSM_DT || (COMPILE_TEST OF ARM)
- k
Yes. That's the version I am going with. I might
file.
- Renamed files to reflect vendor name instead of specific device
- Converted to use (readl|writel)_relaxed w/ appropriate barriers
- Removed unions in favor of standard types.
Andy Gross (2):
dmaengine: add Qualcomm BAM dma driver
dmaengine: qcom_bam_dma: Add
the peripheral and system memory (System mode), or
between two peripherals (BAM2BAM).
The initial release of this driver only supports slave transfers between
peripherals and system memory.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/dma/Kconfig|9 +
drivers/dma/Makefile
Add device tree binding support for the QCOM BAM DMA driver.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
.../devicetree/bindings/dma/qcom_bam_dma.txt | 52
1 file changed, 52 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma
On Tue, Jan 28, 2014 at 10:05:35AM +0100, Lars-Peter Clausen wrote:
On 01/28/2014 07:27 AM, Andy Gross wrote:
Add device tree binding support for the QCOM BAM DMA driver.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
.../devicetree/bindings/dma/qcom_bam_dma.txt | 52
On Tue, Jan 28, 2014 at 10:16:53AM +0100, Arnd Bergmann wrote:
On Tuesday 28 January 2014 10:05:35 Lars-Peter Clausen wrote:
+
+Clients must use the format described in the dma.txt file, using a three
cell
+specifier for each channel.
+
+The three cells in order are:
+ 1. A
Add device tree binding support for the QCOM BAM DMA driver.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
.../devicetree/bindings/dma/qcom_bam_dma.txt | 48
1 file changed, 48 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma
.
- Renamed files to reflect vendor name instead of specific device
- Converted to use (readl|writel)_relaxed w/ appropriate barriers
- Removed unions in favor of standard types.
Andy Gross (2):
dmaengine: add Qualcomm BAM dma driver
dmaengine: qcom_bam_dma: Add device tree binding
the peripheral and system memory (System mode), or
between two peripherals (BAM2BAM).
The initial release of this driver only supports slave transfers between
peripherals and system memory.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/dma/Kconfig|9 +
drivers/dma/Makefile
On Tue, Feb 04, 2014 at 12:58:25PM +0100, Lars-Peter Clausen wrote:
On 02/04/2014 12:04 AM, Andy Gross wrote:
[...]
+static int bam_dma_remove(struct platform_device *pdev)
+{
+struct bam_device *bdev = platform_get_drvdata(pdev);
+u32 i;
+
+dma_async_device_unregister(bdev
the peripheral and system memory (System mode), or
between two peripherals (BAM2BAM).
The initial release of this driver only supports slave transfers between
peripherals and system memory.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/dma/Kconfig|9 +
drivers/dma/Makefile
Add device tree binding support for the QCOM BAM DMA driver.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
.../devicetree/bindings/dma/qcom_bam_dma.txt | 48
1 file changed, 48 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma
On Thu, Feb 06, 2014 at 06:57:47PM +0200, Ivan T. Ivanov wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
The Qualcomm Universal Peripheral (QUP) core is an
AHB slave that provides a common data path (an output
FIFO and an input FIFO) for serial peripheral interface
(SPI) mini-core.
On Fri, Feb 07, 2014 at 11:52:33AM +0200, Ivan T. Ivanov wrote:
Hi Andy,
On Fri, 2014-02-07 at 01:39 -0600, Andy Gross wrote:
On Thu, Feb 06, 2014 at 06:57:48PM +0200, Ivan T. Ivanov wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
Qualcomm Universal Peripheral (QUP) core
On Fri, Feb 07, 2014 at 05:52:34PM +, Mark Brown wrote:
On Fri, Feb 07, 2014 at 11:32:07AM -0600, Andy Gross wrote:
On Fri, Feb 07, 2014 at 11:52:33AM +0200, Ivan T. Ivanov wrote:
[... snip ...]
The platform doesn't have support for PM right now. So it's probably
better
On Mon, Feb 10, 2014 at 06:55:02PM +0200, Ivan T. Ivanov wrote:
[]
Bail here?
I don't know. What will be the consequences if controller continue to
operate on its default rate?
It is unclear. But if you can't set the rate that is configured or if
there is
a
On Tue, Feb 11, 2014 at 11:00:48PM +0530, Vinod Koul wrote:
On Tue, Feb 04, 2014 at 02:42:35PM -0600, Andy Gross wrote:
Add the DMA engine driver for the QCOM Bus Access Manager (BAM) DMA
controller
found in the MSM 8x74 platforms.
[.]
+ * QCOM BAM DMA engine driver
and returns residuals
- Removed proprietary slave config. Removed associated include file.
- Renamed files to reflect vendor name instead of specific device
- Converted to use (readl|writel)_relaxed w/ appropriate barriers
- Removed unions in favor of standard types.
Andy
the peripheral and system memory (System mode), or
between two peripherals (BAM2BAM).
The initial release of this driver only supports slave transfers between
peripherals and system memory.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/dma/Kconfig|9 +
drivers/dma/Makefile
Add device tree binding support for the QCOM BAM DMA driver.
Acked-by: Kumar Gala ga...@codeaurora.org
Signed-off-by: Andy Gross agr...@codeaurora.org
---
.../devicetree/bindings/dma/qcom_bam_dma.txt | 48
1 file changed, 48 insertions(+)
create mode 100644
On Fri, Feb 21, 2014 at 09:26:57AM +, Mark Rutland wrote:
On Fri, Feb 21, 2014 at 06:43:04AM +, Andy Gross wrote:
Add device tree binding support for the QCOM BAM DMA driver.
[snip]
+Required properties:
+- compatible: Must be qcom,bam-v1.4.0 for MSM8974 V1
On Fri, Feb 21, 2014 at 09:33:52AM +, Mark Rutland wrote:
On Fri, Feb 21, 2014 at 06:43:05AM +, Andy Gross wrote:
[snip]
+ bdev-bamclk = devm_clk_get(bdev-dev, bam_clk);
The binding document should describe the bam_clk string in the
clock-names description.
OK
On Fri, Feb 21, 2014 at 05:36:47PM +, Mark Rutland wrote:
[snip]
Yes only a single interrupt. I can remove the s.
Please don't, the interrupts proeprty is standard and shouldn't change.
I was only asking to ensure that all interrupts were described in the
binding, which they are.
the peripheral and system memory (System mode), or
between two peripherals (BAM2BAM).
The initial release of this driver only supports slave transfers between
peripherals and system memory.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/dma/Kconfig|9 +
drivers/dma/Makefile
Add device tree binding support for the QCOM BAM DMA driver.
Acked-by: Kumar Gala ga...@codeaurora.org
Signed-off-by: Andy Gross agr...@codeaurora.org
---
.../devicetree/bindings/dma/qcom_bam_dma.txt | 41
1 file changed, 41 insertions(+)
create mode 100644
On Tue, Feb 25, 2014 at 08:07:13AM -0800, Bjorn Andersson wrote:
[snip]
The v2 model will get BAM (DMAEngine) support soon, v1 uses an
older DMA core. So there's a difference. I'm not aware what differences
there are between 2.1.1 and 2.2.1.
Difference between 2.1.1 and 2.2.1:
- high speed
On Wed, Feb 26, 2014 at 06:51:55PM +0200, Stanimir Varbanov wrote:
+ /* read revision and configuration information */
+ val = readl_relaxed(bdev-regs + BAM_REVISION) NUM_EES_MASK;
+
The ees shit is not zero and you got wrong ee. Could you add the line
below or something similar:
in favor of standard types.
Andy Gross (2):
dmaengine: qcom_bam_dma: Add device tree binding
dmaengine: add Qualcomm BAM dma driver
.../devicetree/bindings/dma/qcom_bam_dma.txt | 41 +
drivers/dma/Kconfig|9 +
drivers/dma/Makefile
Add device tree binding support for the QCOM BAM DMA driver.
Acked-by: Kumar Gala ga...@codeaurora.org
Signed-off-by: Andy Gross agr...@codeaurora.org
---
.../devicetree/bindings/dma/qcom_bam_dma.txt | 41
1 file changed, 41 insertions(+)
create mode 100644
On Sat, Mar 08, 2014 at 12:29:49AM +0200, Stanimir Vabanov wrote:
+#define BAM_IRQ_SRCS_EE(pipe) (0x0800 + ((pipe) * 0x80))
+#define BAM_IRQ_SRCS_MSK_EE(pipe) (0x0804 + ((pipe) * 0x80))
s/pipe/ee ?
Ah good catch. I'll fix that.
+struct bam_chan {
+ struct
On Mon, Mar 03, 2014 at 09:38:03AM +, Shevchenko, Andriy wrote:
snip
+ if (IS_ERR(bdev-bamclk))
+ return PTR_ERR(bdev-bamclk);
+
+ ret = clk_prepare_enable(bdev-bamclk);
+ if (ret) {
+ dev_err(bdev-dev, failed to prepare/enable clock\n);
+
the peripheral and system memory (System mode), or
between two peripherals (BAM2BAM).
The initial release of this driver only supports slave transfers between
peripherals and system memory.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/dma/Kconfig|9 +
drivers/dma/Makefile
.
- Renamed files to reflect vendor name instead of specific device
- Converted to use (readl|writel)_relaxed w/ appropriate barriers
- Removed unions in favor of standard types.
Andy Gross (2):
dmaengine: qcom_bam_dma: Add device tree binding
dmaengine: add Qualcomm BAM
Define a new binding for the Qualcomm TLMMv2 based pin controller inside the
IPQ8064.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
.../bindings/pinctrl/qcom,ipq8064-pinctrl.txt | 95
1 file changed, 95 insertions(+)
create mode 100644
Documentation/devicetree
This adds pinctrl definitions for the GPIO pins of the TLMM v2 block in the
Qualcomm IPQ8064 platform.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/pinctrl/Kconfig |8 +
drivers/pinctrl/Makefile |1 +
drivers/pinctrl/pinctrl-ipq8064.c | 653
different offsets and multipliers that are
specific to that version of the IP block.
Andy Gross (2):
dmaengine: qcom_bam_dma: Add v1.3.0 driver support
dmaengine: qcom_bam_dma: Add binding for v1.3.0
.../devicetree/bindings/dma/qcom_bam_dma.txt |4 +-
drivers/dma/qcom_bam_dma.c
This patch removes direct access of the GSBI registers. GSBI configuration
should be done through the GSBI driver directly.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/tty/serial/msm_serial.c | 48 ++-
drivers/tty/serial/msm_serial.h |5
The GSBI (General Serial Bus Interface) driver controls the overarching
configuration of the shared serial bus infrastructure on APQ8064, IPQ8064, and
earlier QCOM processors. The GSBI supports UART, I2C, SPI, and UIM
functionality in various combinations.
Signed-off-by: Andy Gross agr
Add device tree binding support for the QCOM GSBI driver.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
.../devicetree/bindings/soc/qcom/qcom,gsbi.txt | 78
1 file changed, 78 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom
mode setting for the ports and keep the children
from accessing the GSBI directly.
Andy Gross (4):
soc: Placeholder files for drivers/soc
soc: qcom: Add GSBI driver
soc: qcom: Add device tree binding for GSBI
tty: serial: msm: Remove direct access to GSBI
.../devicetree/bindings/soc/qcom
On Mon, Apr 21, 2014 at 11:54:00AM -0500, Josh Cartwright wrote:
snip
+
+struct gsbi_dev {
+ struct device *dev;
+ void __iomem*base;
You don't really need these.
Old habits die hard. I'll remove.
snip
+ if (of_property_read_u32(node, qcom,mode, mode)) {
+
This patch adds pin definitiones for the MSM8x74 TLMM. New definitions
include:
BLSP devices (I2C, UART, UART flow control, SPI, and UIM), mi2s, gp clk, pdm,
gcc clk, cci_timer, cci_i2c, cam_clk, hsic, tsif, sdc3, sdc4, and other assorted
pins.
Signed-off-by: Andy Gross agr...@codeaurora.org
This patch corrects the error check on the call to pm_runtime_get_sync.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/i2c/busses/i2c-qup.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/i2c/busses/i2c-qup.c b/drivers/i2c/busses/i2c-qup.c
index 1b4cf14
On Fri, May 09, 2014 at 10:37:00AM +0200, Linus Walleij wrote:
On Fri, May 2, 2014 at 6:44 AM, Andy Gross agr...@codeaurora.org wrote:
This patch adds pin definitiones for the MSM8x74 TLMM. New definitions
include:
BLSP devices (I2C, UART, UART flow control, SPI, and UIM), mi2s, gp clk
This patch adds pin definitiones for the MSM8x74 TLMM. New definitions
include:
BLSP devices (I2C, UART, UART flow control, SPI, and UIM), mi2s, gp clk, pdm,
gcc clk, cci_timer, cci_i2c, cam_clk, hsic, tsif, sdc3, sdc4, and other assorted
pins.
Signed-off-by: Andy Gross agr...@codeaurora.org
On Fri, May 09, 2014 at 01:08:25PM -0500, Kumar Gala wrote:
Drop underscore in spdif_groups to match all other groups.
Signed-off-by: Kumar Gala ga...@codeaurora.org
Reviewed-by: Andy Gross agr...@codeaurora.org
snip
--
sent by an employee of the Qualcomm Innovation Center, Inc
This patch adds pin definitiones for the MSM8x74 TLMM. New definitions
include:
BLSP devices (I2C, UART, SPI, and UIM), mi2s, gp clk, pdm, gcc clk, cci_timer,
cci_i2c, cam_clk, hsic, tsif, sdc3, sdc4, and other assorted pins.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
.../bindings
This patch fixes the calculation for determining whether to use FIFO or BLOCK
mode.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/spi/spi-qup.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
index ea7017b
to be called after the runtime
pm is initialized.
The last patch adds support for V1.1.1 of the QUP. This version of the
controller is present in earlier devices (APQ8064, IPQ8064, and MSM8960).
Andy Gross (4):
spi: qup: Remove chip select function
spi: qup: Correct selection of FIFO/Block mode
This patch removes the chip select function. Chip select should instead be
supported using GPIOs, defining the DT entry cs-gpios, and letting the SPI
core assert/deassert the chip select as it sees fit.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
.../devicetree/bindings/spi/qcom,spi
This patch moves the devm_spi_register_master below the initialization of the
runtime_pm. If done in the wrong order, the spi_register_master fails if any
probed slave devices issue SPI transactions.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/spi/spi-qup.c | 11 +++
1
This patch adds support for v1.1.1 of the SPI QUP controller.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/spi/spi-qup.c | 32
1 file changed, 20 insertions(+), 12 deletions(-)
diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
index
On Tue, May 13, 2014 at 03:08:45PM -0700, Stephen Boyd wrote:
On 05/13, Andy Gross wrote:
@@ -488,7 +491,7 @@ static int spi_qup_probe(struct platform_device *pdev)
struct resource *res;
struct device *dev;
void __iomem *base;
- u32 data, max_freq, iomode;
+ u32 data
On Fri, May 02, 2014 at 01:08:27PM -0500, Andy Gross wrote:
On Fri, May 02, 2014 at 09:58:41PM +0530, Vinod Koul wrote:
On Thu, Apr 17, 2014 at 05:04:02PM -0500, Andy Gross wrote:
This patch adds APIs that allow for BAM hardware flags to be set per
descriptor. Each one of the new flags
On Thu, May 22, 2014 at 11:40:49AM +0530, Vinod Koul wrote:
snip
I have 3 different IRQs that can be asserted based on the bit I set in the
hardware descriptor. The normal IRQ is the INT bit. However, in some
cases the
peripheral protocol requires the use of the EOT or EOB
On Thu, May 22, 2014 at 04:27:05PM +0100, Srinivas Kandagatla wrote:
snip
The EOT is not used for every transaction. It is part of a handshaking
protocol with the attached peripheral, much like the NWD (notify when done).
As
near as I can tell today, no peripheral depends on the EOB, so
DMA_PREP_FENCE to enable this flag.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/dma/qcom_bam_dma.c | 20 ++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/drivers/dma/qcom_bam_dma.c b/drivers/dma/qcom_bam_dma.c
index e01c2d106..4635224 100644
--- a/drivers
On Tue, Jun 10, 2014 at 10:39:02AM -0700, Stephen Boyd wrote:
snip
diff --git a/drivers/soc/qcom/qcom_gsbi.c b/drivers/soc/qcom/qcom_gsbi.c
index ab7b441..64fb298 100644
--- a/drivers/soc/qcom/qcom_gsbi.c
+++ b/drivers/soc/qcom/qcom_gsbi.c
@@ -22,44 +22,63 @@
#define GSBI_CTRL_REG
On Tue, Jun 10, 2014 at 06:47:29PM +0100, Srinivas Kandagatla wrote:
snip
What does mode and crci have to do with this patch? Can't we just put
the clock into the platform data?
It has nothing to do with this but, for completeness and we might
need this if we are doing PM in future. for
On Mon, May 19, 2014 at 11:07:38AM +0300, Ivan T. Ivanov wrote:
snip
+- num-cs: total number of chipselects
My understanding is that num-cs have to be parsed by
master driver, not by core SPI driver.
Right. I need to parse it and check vs the max cs and use that value to set the
This patch adds support for v1.1.1 of the SPI QUP controller.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
.../devicetree/bindings/spi/qcom,spi-qup.txt |6 +++-
drivers/spi/spi-qup.c | 36
2 files changed, 27 insertions(+), 15
This patch moves the devm_spi_register_master below the initialization of the
runtime_pm. If done in the wrong order, the spi_register_master fails if any
probed slave devices issue SPI transactions.
Signed-off-by: Andy Gross agr...@codeaurora.org
Acked-by: Ivan T. Ivanov iiva...@mm-sol.com
, IPQ8064, and MSM8960).
Andy Gross (3):
spi: qup: Remove chip select function
spi: qup: Fix order of spi_register_master
spi: qup: Add support for v1.1.1
.../devicetree/bindings/spi/qcom,spi-qup.txt | 12 ++-
drivers/spi/spi-qup.c | 80
This patch adds the BUS_HOLD (Keeper) bias option for pins.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/pinctrl/pinctrl-msm.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-msm.c b/drivers/pinctrl/pinctrl-msm.c
index e43fbce..9aa2839 100644
(client rate
control interface) is supported and can be configured via device tree
configuration. Flow control usage is required for some peripheral devices.
Andy Gross (2):
dmaengine: Add QCOM ADM DMA driver
dmaengine: qcom_adm: Add device tree binding
Documentation/devicetree/bindings/dma
Add device tree binding support for the QCOM ADM DMA driver.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
Documentation/devicetree/bindings/dma/qcom_adm.txt | 60
1 file changed, 60 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/qcom_adm.txt
This patch adds DMA capabilities to the spi-qup driver. If DMA channels are
present, the QUP will use DMA instead of block mode for transfers to/from SPI
peripherals for transactions larger than the length of a block.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
.../devicetree/bindings
On Fri, Jun 27, 2014 at 11:50:57AM +0100, Mark Brown wrote:
On Thu, Jun 26, 2014 at 04:06:21PM -0500, Andy Gross wrote:
+ if (xfer-rx_buf) {
+ rx_dma = dma_map_single(controller-dev, xfer-rx_buf,
+ xfer-len, DMA_FROM_DEVICE);
It would be better to use
On Fri, Jun 27, 2014 at 05:24:11PM +0100, Russell King - ARM Linux wrote:
snip
It would be better to use the core DMA mapping code rather than open
coding. This code won't work for vmalloc()ed addresses, or physically
non-contiguous addresses unless there's an IOMMU fixing things up.
-by: Andy Gross agr...@codeaurora.org
---
drivers/usb/phy/Kconfig | 11 ++
drivers/usb/phy/Makefile |2 +
drivers/usb/phy/phy-qcom-hsusb.c | 348 ++
drivers/usb/phy/phy-qcom-ssusb.c | 385 ++
4 files changed
These patches add basic support for USB3.0 controllers found
on MSM platforms. USB3.0 core is based on Synopsys DesignWare
SuperSpeed IP.
This work was started by Ivan Ivanov and went through a number of iterations. I
picked these patches up and did a little rework to get them working.
From: Ivan T. Ivanov iiva...@mm-sol.com
DWC3 glue layer is hardware layer around Synopsys DesignWare
USB3 core. Its purpose is to supply Synopsys IP with required
clocks, voltages and interface it with the rest of the SoC.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
Signed-off-by: Andy
-off-by: Andy Gross agr...@codeaurora.org
---
.../devicetree/bindings/usb/qcom,dwc3.txt | 104
1 file changed, 104 insertions(+)
create mode 100644 Documentation/devicetree/bindings/usb/qcom,dwc3.txt
diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.txt
b
On Tue, Jul 01, 2014 at 12:04:35AM -0500, Rob Herring wrote:
snip
+- clock-names: Should contain the following:
+ core Master/Core clock, have to be = 125 MHz for SS
+ operation and = 60MHz for HS operation
+
+Optional clocks:
+ iface
On Thu, Jul 17, 2014 at 06:30:24AM -0400, kiran.pad...@smartplayin.com wrote:
Hi,
On Mon, Jun 30, 2014 at 9:33 PM, Andy Gross agr...@codeaurora.org wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
These drivers handles control and configuration of the HS
and SS USB PHY transceivers
On Mon, Jul 14, 2014 at 10:06:16PM +0530, Vinod Koul wrote:
On Fri, May 30, 2014 at 03:49:50PM -0500, Andy Gross wrote:
This patch adds support for end of transaction (EOT) and notify when done
(NWD)
hardware descriptor flags.
The EOT flag requests that the peripheral assert an end
This patch adds a MAINTAINERS entry for the SOC Qualcomm drivers.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index aefa948..3ad0a26 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8426,6
On Tue, Aug 19, 2014 at 09:39:30PM -0700, Bjorn Andersson wrote:
On Tue 19 Aug 10:22 PDT 2014, Georgi Djakov wrote:
This patch adds support for the TLMM (Top-Level Mode Mux) block found
in the APQ8084 platform.
[...]
+
+#define NUM_GPIO_PINGROUPS 143
+
I think this looks good
On Tue, Aug 19, 2014 at 08:22:14PM +0300, Georgi Djakov wrote:
This patch adds support for the TLMM (Top-Level Mode Mux) block found
in the APQ8084 platform.
Comment in-line
snip
+ PINCTRL_PIN(134, GPIO_134),
+ PINCTRL_PIN(135, GPIO_135),
+ PINCTRL_PIN(136, GPIO_136),
+
On Tue, Aug 26, 2014 at 03:45:54PM +0300, Georgi Djakov wrote:
This patchset adds pinctrl support for the Qualcomm APQ8084 platform.
Signed-off-by: Georgi Djakov gdja...@mm-sol.com
Looks good. I'll try to test this tomorrow, but for now
Reviewed-by: Andy Gross agr...@codeaurora.org
On Tue, Aug 26, 2014 at 03:45:55PM +0300, Georgi Djakov wrote:
Define a new binding for the Qualcomm TLMM (Top-Level Mode Mux) based pin
controller inside the APQ8084.
Signed-off-by: Georgi Djakov gdja...@mm-sol.com
Looks fine.
Reviewed-by: Andy Gross agr...@codeaurora.org
--
sent
Add device tree binding support for the QCOM ADM DMA driver.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
Documentation/devicetree/bindings/dma/qcom_adm.txt | 62
1 file changed, 62 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/qcom_adm.txt
for transactions to/from peripheral devices.
The initial release of this driver supports slave transfers to/from peripherals
and also incorporates CRCI (client rate control interface) flow control.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/dma/Kconfig| 10 +
drivers/dma/Makefile
will only support slave DMA operations
between system memory and peripherals. Flow control via the CRCI (client rate
control interface) is supported and can be configured via device tree
configuration. Flow control usage is required for some peripheral devices.
Andy Gross (2):
dmaengine: Add QCOM
This patch adds a new driver for the Qualcomm USB 3.0 PHY that exists on some
Qualcomm platforms. This driver uses the generic PHY framework and will
interact with the DWC3 controller.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/phy/Kconfig | 11 +
drivers/phy/Makefile
description
* Disable regulators in glue layer if there is error during
ioremap.
Changes since first version:
* Split devicetree bindings description file to separate patch
* Address comments for device bindings description
* Fix typo in 'gdsc' requlator name.
Andy Gross (1):
phy: Add Qualcomm
From: Ivan T. Ivanov iiva...@mm-sol.com
DWC3 glue layer is hardware layer around Synopsys DesignWare
USB3 core. Its purpose is to supply Synopsys IP with required
clocks, voltages and interface it with the rest of the SoC.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
Signed-off-by: Andy
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