On 11/9/2015 2:15 AM, Hannes Reinecke wrote:
On 11/09/2015 02:57 AM, Sinan Kaya wrote:
The mpt2sas and mpt3sas drivers are spinning forever in
their IRQ handlers if there are a lot of jobs queued up
by the PCIe card. This handler is causing spikes for
the rest of the system and sluggish
On 11/9/2015 2:09 AM, Hannes Reinecke wrote:
On 11/09/2015 02:57 AM, Sinan Kaya wrote:
Current code gives up when 32 bit DMA is not supported.
This problem has been observed on systems without any
memory below 4 gig.
This patch tests 64 bit support before bailing out to find
a working
On 11/9/2015 3:59 AM, Arnd Bergmann wrote:
On Monday 09 November 2015 08:09:39 Hannes Reinecke wrote:
On 11/09/2015 02:57 AM, Sinan Kaya wrote:
Current code gives up when 32 bit DMA is not supported.
This problem has been observed on systems without any
memory below 4 gig.
This patch tests
or PCIe. SBSA requires all inbound PCIe
addresses to be non-translated.
I'll just have to stick with IOMMU for this card.
--
Sinan Kaya
Qualcomm Technologies, Inc. on behalf of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a
Linux Foundation
On 11/10/2015 1:27 PM, James Bottomley wrote:
On Tue, 2015-11-10 at 12:19 -0500, Sinan Kaya wrote:
On 11/10/2015 11:47 AM, Arnd Bergmann wrote:
On Tuesday 10 November 2015 11:06:40 Sinan Kaya wrote:
On 11/10/2015 3:38 AM, Arnd Bergmann wrote:
From the email thread, it looks like
On 11/10/2015 11:47 AM, Arnd Bergmann wrote:
On Tuesday 10 November 2015 11:06:40 Sinan Kaya wrote:
On 11/10/2015 3:38 AM, Arnd Bergmann wrote:
> No, as Timur found, the driver is correct and it intentionally
sets the 32-bit mask, and that is guaranteed to work on all sane
hardware. Do
do 64 bit DMA when IOMMU is not
there. I need IOMMU enabled all the time for this card.
--
Sinan Kaya
Qualcomm Technologies, Inc. on behalf of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a
Linux Foundation Collaborative Project
s
parametrising issues with particular hardware. There's no software work
around (except allocating memory with the correct characteristics).
Need confirmation. I'm questioning if we are stuck with this behavior
because of altix or something else. If the latter case, the code could
have used PCI ID
device is in IOMMU translation mode.
Details are in the IORT spec.
--
Sinan Kaya
Qualcomm Technologies, Inc. on behalf of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a
Linux Foundation Collaborative Project
--
To unsubscribe from this list
On 11/9/2015 10:26 PM, Timur Tabi wrote:
Sinan Kaya wrote:
I created this patch back in March with an older version of the compiler
and older kernel (3.19). I'm no longer able to reproduce this with this
compiler and linux-next.
Thread model: posix
gcc version 4.8.3 20140401 (prerelease
On 11/9/2015 8:48 AM, Timur Tabi wrote:
Sinan Kaya wrote:
And why kmalloc anyway? Why not leave it on the stack?
char src[] = "hello world";
?
I need to call dma_map_single on this address to convert it to a DMA
address. That's why.
And you can't do that with an obj
On 11/9/2015 4:26 AM, Andy Shevchenko wrote:
On Mon, Nov 9, 2015 at 5:07 AM, Sinan Kaya <ok...@codeaurora.org> wrote:
On 11/8/2015 3:09 PM, Andy Shevchenko wrote:
On Sun, Nov 8, 2015 at 6:52 AM, Sinan Kaya <ok...@codeaurora.org> wrote:
This patch adds supporting utili
On 11/9/2015 1:25 PM, Rob Herring wrote:
On Sun, Nov 08, 2015 at 09:17:20PM -0500, Sinan Kaya wrote:
On 11/8/2015 12:08 AM, Timur Tabi wrote:
On 11/8/2015 12:08 AM, Timur Tabi wrote:
Sinan Kaya wrote:
+val = val & ~(MAX_BUS_REQ_LEN_MASK << MAX_BUS_WR_REQ_BIT_POS);
+
On 11/9/2015 2:15 AM, Hannes Reinecke wrote:
On 11/09/2015 02:57 AM, Sinan Kaya wrote:
The mpt2sas and mpt3sas drivers are spinning forever in
their IRQ handlers if there are a lot of jobs queued up
by the PCIe card. This handler is causing spikes for
the rest of the system and sluggish
On 11/9/2015 8:50 AM, Timur Tabi wrote:
Sinan Kaya wrote:
I'm concerned about this though since you warned. This used to consume
1024 bytes now 4096 bytes.
static int acpi_irq_penalty[ACPI_MAX_IRQS] = {
PIRQ_PENALTY_ISA_ALWAYS,/* IRQ0 timer */
...
}
As long as it's not ever put
esource and devm_ioremap_resource together.
Which one do you want me to remove?
--
Sinan Kaya
Qualcomm Technologies, Inc. on behalf of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a
Linux Foundation Collaborative Project
--
To unsubscr
return 0;
}
bool hidma_ll_isenabled(struct hidma_lldev *lldev)
Seems rather pointless, what about 'static void ...' and dropping the
return statement?
Daniel K.
Yes, that's what I ended up doing. rc was forgotten there because I had
to restructure code to use the issue_pending API
The MULDIV macro has been designed for small numbers.
Compiler emits an overflow warning on 64 bit systems.
This patch uses 64 bit numbers in order to suppress
warning.
Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
---
drivers/scsi/sg.c | 20 +---
1 file changed, 13 inse
context. This relexes the rest
of the system execution.
Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
---
drivers/scsi/mpt2sas/mpt2sas_base.c | 12
drivers/scsi/mpt3sas/mpt3sas_base.c | 13 +
2 files changed, 17 insertions(+), 8 deletions(-)
diff --git a/driver
Current code gives up when 32 bit DMA is not supported.
This problem has been observed on systems without any
memory below 4 gig.
This patch tests 64 bit support before bailing out to find
a working combination.
Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
---
drivers/scsi/m
* None
Sinan Kaya (3):
scsi: mptxsas: try 64 bit DMA when 32 bit DMA fails
scsi: fix compiler warning for sg
scsi: mptxsas: offload IRQ execution
drivers/scsi/mpt2sas/mpt2sas_base.c | 33 -
drivers/scsi/mpt3sas/mpt3sas_base.c | 35
On 11/8/2015 12:08 AM, Timur Tabi wrote:
On 11/8/2015 12:08 AM, Timur Tabi wrote:
Sinan Kaya wrote:
+val = val & ~(MAX_BUS_REQ_LEN_MASK << MAX_BUS_WR_REQ_BIT_POS);
+val = val | (mgmtdev->max_write_request << MAX_BUS_WR_REQ_BIT_POS);
+val = val & ~(MAX_BUS_
On 11/8/2015 2:13 PM, kbuild test robot wrote:
Hi Sinan,
[auto build test WARNING on: robh/for-next]
[also build test WARNING on: v4.3 next-20151106]
url:
https://github.com/0day-ci/linux/commits/Sinan-Kaya/ma-add-Qualcomm-Technologies-HIDMA-driver/20151108-125824
base: https
On 11/8/2015 12:13 AM, Timur Tabi wrote:
Sinan Kaya wrote:
+static int dma_selftest_sg(struct dma_device *dmadev,
+struct dma_chan *dma_chanptr, u64 size,
+unsigned long flags)
+{
+dma_addr_t src_dma, dest_dma, dest_dma_it;
+u8 *dest_buf;
+u32 i, j = 0
On 11/8/2015 11:11 AM, Timur Tabi wrote:
Sinan Kaya wrote:
-#define ACPI_MAX_IRQS256
+#define ACPI_MAX_IRQS1020
Why 1020? Why not 1024?
1020 is the maximum interrupt ID that can be directed to an ARM SPI
interrupt according to ARM architecture.
--
Sinan Kaya
Qualcomm
On 11/8/2015 3:47 PM, Andy Shevchenko wrote:
On Sun, Nov 8, 2015 at 6:53 AM, Sinan Kaya <ok...@codeaurora.org> wrote:
This patch adds support for hidma engine. The driver
consists of two logical blocks. The DMA engine interface
and the low-level interface. The hardware only supports
since you warned. This used to consume
1024 bytes now 4096 bytes.
static int acpi_irq_penalty[ACPI_MAX_IRQS] = {
PIRQ_PENALTY_ISA_ALWAYS,/* IRQ0 timer */
...
}
Sinan
--
Sinan Kaya
Qualcomm Technologies, Inc. on behalf of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Ce
This patch adds support for hidma engine. The driver consists
of two logical blocks. The DMA engine interface and the
low-level interface. The hardware only supports memcpy/memset
and this driver only support memcpy interface. HW and driver
doesn't support slave interface.
Signed-off-by: Sinan
driver is executed in hypervisor context and
is the main management entity for all channels provided by
the device.
Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
---
.../devicetree/bindings/dma/qcom_hidma_mgmt.txt| 61
drivers/dma/qcom/Kconfig | 11 +
d
Creating a QCOM directory for all QCOM DMA source
files.
Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
---
drivers/dma/Kconfig| 11 ++-
drivers/dma/Makefile | 2 +-
drivers/dma/qcom/Kconfig
This patch adds supporting utility functions for selftest.
The intention is to share the self test code between
different drivers.
Supported test cases include:
1. dma_map_single
2. streaming DMA
3. coherent DMA
4. scatter-gather DMA
Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
---
d
* remove the checks after platform_get_resource.
* reorder the pm calls in failure path.
* simplify bit clear and set operations.
* correct device tree documentation compatible string
* clean unnecessary initializations and use unsigned int for
iterator types
Sinan Kaya (4):
dma: qcom_bam_dma: move
an upper limit of 1020 as possible
interrupt id.
1020 is the maximum interrupt ID that can be assigned to
an ARM SPI interrupt according to ARM architecture.
Additional checks have been placed to prevent out of bounds
writes.
Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
---
driver
ifferent from PCIe SRIOV passthrough.
Pinning guest removes use cases like ballooning/overcommit but that is a
choice for end user to make: whether he wants additional I/O performance
or wants higher memory utilization at the cost of lower I/O performance.
--
Sinan Kaya
Qualcomm Technologies,
On 11/12/2015 4:53 AM, Andy Shevchenko wrote:
> On Thu, Nov 12, 2015 at 8:41 AM, Sinan Kaya <ok...@codeaurora.org> wrote:
>> The Qualcomm Technologies HIDMA device has been designed
>> to support virtualization technology. The driver has been
>> divided into two to
driver is executed in hypervisor context and
is the main management entity for all channels provided by
the device.
Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
---
.../devicetree/bindings/dma/qcom_hidma_mgmt.txt| 61
drivers/dma/qcom/Kconfig | 10 +
d
This patch adds support for hidma engine. The driver consists
of two logical blocks. The DMA engine interface and the
low-level interface. The hardware only supports memcpy/memset
and this driver only support memcpy interface. HW and driver
doesn't support slave interface.
Signed-off-by: Sinan
Creating a QCOM directory for all QCOM DMA source files.
Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
---
drivers/dma/Kconfig| 11 ++-
drivers/dma/Makefile | 2 +-
drivers/dma/qcom/Kconfig
variable names where possible.
* remove error check after platform_get_resource
* return the error code from device read functions
Changes from V4: (https://lkml.org/lkml/2015/11/12/19)
* remove dev_dbg messages
* seperate selftest code from the series
Sinan Kaya (3):
dma: qcom_bam_dma: move to qcom
Changes from V4 (https://lkml.org/lkml/2015/11/12/18)
* Seperate the series from HIDMA driver
Sinan Kaya (2):
dmaselftest: add memcpy selftest support functions
dma: qcom_hidma: add self test hooks
drivers/dma/dmaengine.h | 2 +
drivers/dma/dmaselftest.c | 638
This patch adds supporting utility functions for selftest.
The intention is to share the self test code between
different drivers.
Supported test cases include:
1. dma_map_single
2. streaming DMA
3. coherent DMA
4. scatter-gather DMA
Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
---
d
of the compiler
and older kernel (3.19). I'm no longer able to reproduce this with this
compiler and linux-next.
Thread model: posix
gcc version 4.8.3 20140401 (prerelease) (crosstool-NG
linaro-1.13.1-4.8-2014.04 - Linaro GCC 4.8-2014.04)
I'll drop this patch.
--
Sinan Kaya
Qualcomm Technologies, Inc
On 11/9/2015 1:19 PM, Rob Herring wrote:
On Sat, Nov 07, 2015 at 11:53:00PM -0500, Sinan Kaya wrote:
This patch adds support for hidma engine. The driver
consists of two logical blocks. The DMA engine interface
and the low-level interface. The hardware only supports
memcpy/memset
Creating a QCOM directory for all QCOM DMA
source files.
Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
---
drivers/dma/Kconfig| 13 +-
drivers/dma/Makefile |2 +-
drivers/dma/qcom/Kconfig |9 +
drivers/dma/qcom/Makefile |1 +
drivers/dma/qcom/bam_dma.c
han one tasklet
per completion. Completions are queued into kfifo and consumed
by a single tasklet.
* Move start of actual transfer to issue_pending
* Simplify return path when DMA mask set fails.
* Move code to qcom directory.
Sinan Kaya (4):
dma: qcom_bam_dma: move to qcom directory
dma: a
.
The management driver is executed in hypervisor context and
is the main management entity for all channels provided by
the device.
Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
---
.../devicetree/bindings/dma/qcom_hidma_mgmt.txt| 62
drivers/dma/qcom/K
This patch adds support for hidma engine. The driver
consists of two logical blocks. The DMA engine interface
and the low-level interface. The hardware only supports
memcpy/memset and this driver only support memcpy
interface. HW and driver doesn't support slave interface.
Signed-off-by: Sinan
On 12/5/2015 2:58 AM, Vinod Koul wrote:
> On Tue, Dec 01, 2015 at 11:57:34PM -0500, Sinan Kaya wrote:
>> On 11/30/2015 10:17 PM, Vinod Koul wrote:
>>> On Mon, Nov 30, 2015 at 09:42:01AM -0500, Sinan Kaya wrote:
>>>
>>>>>> +static int
On 12/5/2015 3:00 AM, Vinod Koul wrote:
> On Wed, Dec 02, 2015 at 02:04:05PM -0500, Sinan Kaya wrote:
>>>>> You are missing the point. Channel can be paused, yes but the descriptor
>>>>> is in queue and is not paused. The descriptor running is paused, yes.
>>
On 12/1/2015 4:16 PM, Sinan Kaya wrote:
>>>> >>>
>>>>> >>>> +static enum dma_status hidma_tx_status(struct dma_chan *dmach,
>>>>> >>>> +dma_cookie_t cookie, struct dma_tx_state
>>>>> &
On 12/1/2015 6:34 AM, Vinod Koul wrote:
> On Mon, Nov 30, 2015 at 03:06:36PM -0500, Sinan Kaya wrote:
>> I have split the debugfs support from this patch to its own patch. Any
>> other idea on how else you'd break the code? I can take one more step
>> and separate the lower la
driver is executed in hypervisor context and is the main
management entity for all channels provided by the device.
Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
Reviewed-by: Andy Shevchenko <andy.shevche...@gmail.com>
---
.../ABI/testing/sysfs-platform-hidma-mgmt
This patch adds support for hidma engine. The driver consists of two
logical blocks. The DMA engine interface and the low-level interface.
The hardware only supports memcpy/memset and this driver only support
memcpy interface. HW and driver doesn't support slave interface.
Signed-off-by: Sinan
asynchronous job
queued and completed at a given time.
Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
---
drivers/dma/qcom/Makefile| 2 +-
drivers/dma/qcom/hidma.c | 3 +
drivers/dma/qcom/hidma.h | 2 +
drivers/dma/qcom/hidma_dbg.c | 219
Creating a QCOM directory for all QCOM DMA source files.
Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
Reviewed-by: Andy Gtoss <agr...@codeaurora.org>
---
drivers/dma/Kconfig| 11 ++-
drivers/dma/Makefile | 2 +-
driv
.
Completions are delivered via callbacks via tasklet.
Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
---
drivers/dma/qcom/Makefile | 2 +
drivers/dma/qcom/hidma.c| 2 +-
drivers/dma/qcom/hidma_ll.c | 927
3 files changed, 930 insertions(+), 1 de
assignment.
* tx_status changes to handle completed transactions right before the
pause.
* terminate the running transactions in channel free.
Sinan Kaya (5):
dma: qcom_bam_dma: move to qcom directory
dma: add Qualcomm Technologies HIDMA management driver
dma: add Qualcomm Technologies HIDMA
On 11/30/2015 10:17 PM, Vinod Koul wrote:
> On Mon, Nov 30, 2015 at 09:42:01AM -0500, Sinan Kaya wrote:
>
>>>> +static int hidma_mgmt_probe(struct platform_device *pdev)
>>>> +{
>>>> + struct hidma_mgmt_dev *mgmtdev;
>>>> + struct resource
On 12/5/2015 3:00 AM, Vinod Koul wrote:
> On Wed, Dec 02, 2015 at 02:04:05PM -0500, Sinan Kaya wrote:
>>>>> You are missing the point. Channel can be paused, yes but the descriptor
>>>>> is in queue and is not paused. The descriptor running is paused, yes.
>>
This patch adds support for hidma engine. The driver consists of two
logical blocks. The DMA engine interface and the low-level interface.
The hardware only supports memcpy/memset and this driver only support
memcpy interface. HW and driver doesn't support slave interface.
Signed-off-by: Sinan
Creating a QCOM directory for all QCOM DMA source files.
Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
Reviewed-by: Andy Gtoss <agr...@codeaurora.org>
---
drivers/dma/Kconfig| 11 ++-
drivers/dma/Makefile | 2 +-
driv
.
Completions are delivered via callbacks via tasklet.
Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
---
drivers/dma/qcom/Makefile | 2 +
drivers/dma/qcom/hidma.c| 2 +-
drivers/dma/qcom/hidma_ll.c | 927
3 files changed, 930 insertions(+), 1 de
/3/20)
* Change the pause behavior. Only the running descriptor gets
DMA_PAUSED return code. All others get DMA_IN_PROGRESS.
Changes from V8: (https://lkml.org/lkml/2015/12/3/22)
* none
Changes from V8: (https://lkml.org/lkml/2015/12/3/21)
* none
Sinan Kaya (5):
dma: qcom_bam_dma: move to qcom
driver is executed in hypervisor context and is the main
management entity for all channels provided by the device.
Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
Reviewed-by: Andy Shevchenko <andy.shevche...@gmail.com>
---
.../ABI/testing/sysfs-platform-hidma-mgmt
asynchronous job
queued and completed at a given time.
Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
---
drivers/dma/qcom/Makefile| 2 +-
drivers/dma/qcom/hidma.c | 3 +
drivers/dma/qcom/hidma.h | 2 +
drivers/dma/qcom/hidma_dbg.c | 219
he association is the other way around. User need to know the
management interface for a channel rather than the channel needing to
know the management interface.
I'll think about it.
>
> How can your sysfs interface work if that relationship is not described?
Here is the sysfs documentation
, hidma_00 doesn't get
probed.
hidmam_00: hidma-mgmt@0x5800 {
compatible = "qcom,hidma_mgmt-1.0";
hidma_00: hidma@0x5801 {
compatible = "qcom,hidma-1.0";
}
}
If I put them seperately, it works
hidma_0
/lkml/2015/12/11/587)
* none
Sinan Kaya (7):
dma: qcom_bam_dma: move to qcom directory
dma: hidma: Add Device Tree support
dma: add Qualcomm Technologies HIDMA management driver
dma: add Qualcomm Technologies HIDMA channel driver
dma: qcom_hidma: implement lower level hardware interface
Add documentation for the Qualcomm Technologies HIDMA driver.
Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
---
.../devicetree/bindings/dma/qcom_hidma_mgmt.txt| 79 ++
1 file changed, 79 insertions(+)
create mode 100644 Documentation/devicetree/bindin
asynchronous job
queued and completed at a given time.
Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
---
drivers/dma/qcom/Makefile| 2 +-
drivers/dma/qcom/hidma.c | 3 +
drivers/dma/qcom/hidma.h | 2 +
drivers/dma/qcom/hidma_dbg.c | 219
driver is executed in hypervisor context and is the main
management entity for all channels provided by the device.
Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
Reviewed-by: Andy Shevchenko <andy.shevche...@gmail.com>
---
.../ABI/testing/sysfs-platform-hidma-mgmt | 97
.
Completions are delivered via callbacks via tasklet.
Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
---
drivers/dma/qcom/Makefile | 2 +
drivers/dma/qcom/hidma.h| 2 +-
drivers/dma/qcom/hidma_ll.c | 927
3 files changed, 930 insertions(+), 1 de
This patch adds support for hidma engine. The driver consists of two
logical blocks. The DMA engine interface and the low-level interface.
The hardware only supports memcpy/memset and this driver only support
memcpy interface. HW and driver doesn't support slave interface.
Signed-off-by: Sinan
compatible = "qcom,hidma-1.0";
...
}
}
The hidma_mgmt_init detects each instance of the hidma-mgmt-1.0 objects
in device tree and calls into the channel driver to create platform devices
for each child of the management object.
Signed-off-by: Sinan Kaya &
On 12/11/2015 4:35 AM, Vinod Koul wrote:
> On Thu, Dec 10, 2015 at 03:10:48PM -0500, Sinan Kaya wrote:
>> On 12/5/2015 3:00 AM, Vinod Koul wrote:
>>> On Wed, Dec 02, 2015 at 02:04:05PM -0500, Sinan Kaya wrote:
>>>>>>> You are missing the point. Channe
Hi Mark,
On 12/11/2015 11:41 AM, Mark Rutland wrote:
> Hi,
>
> On Fri, Dec 11, 2015 at 11:16:58AM -0500, Sinan Kaya wrote:
>> The Qualcomm Technologies HIDMA device has been designed to support
>> virtualization technology. The driver has been divided into two to follow
&
Creating a QCOM directory for all QCOM DMA source files.
Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
Reviewed-by: Andy Gtoss <agr...@codeaurora.org>
---
drivers/dma/Kconfig| 11 ++-
drivers/dma/Makefile | 2 +-
driv
Hi Vinod,
On 1/3/2016 7:06 PM, Sinan Kaya wrote:
> The Qualcomm Technologies HIDMA device has been designed
> to support virtualization technology. The driver has been
> divided into two to follow the hardware design.
>
> 1. HIDMA Management driver
> 2. HIDMA Channel driver
.
Completions are delivered via callbacks via tasklet.
Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
---
drivers/dma/qcom/Makefile | 2 +
drivers/dma/qcom/hidma.h| 2 +-
drivers/dma/qcom/hidma_ll.c | 927
3 files changed, 930 insertions(+), 1 de
driver is executed in hypervisor context and is the main
management entity for all channels provided by the device.
Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
Reviewed-by: Andy Shevchenko <andy.shevche...@gmail.com>
---
.../ABI/testing/sysfs-platform-hidma-mgmt | 97
compatible = "qcom,hidma-1.0";
...
}
}
The hidma_mgmt_init detects each instance of the hidma-mgmt-1.0 objects
in device tree and calls into the channel driver to create platform devices
for each child of the management object.
Signed-off-by: Sinan Kaya &
asynchronous job
queued and completed at a given time.
Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
---
drivers/dma/qcom/Makefile| 2 +-
drivers/dma/qcom/hidma.c | 3 +
drivers/dma/qcom/hidma.h | 2 +
drivers/dma/qcom/hidma_dbg.c | 219
This patch adds support for hidma engine. The driver consists of two
logical blocks. The DMA engine interface and the low-level interface.
The hardware only supports memcpy/memset and this driver only support
memcpy interface. HW and driver doesn't support slave interface.
Signed-off-by: Sinan
Add documentation for the Qualcomm Technologies HIDMA driver.
Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
Acked-by: Rob Herring <r...@kernel.org>
---
.../devicetree/bindings/dma/qcom_hidma_mgmt.txt| 79 ++
1 file changed, 79 insertions(+)
create
On 1/3/2016 10:36 PM, Vinod Koul wrote:
> On Sun, Jan 03, 2016 at 07:09:23PM -0500, Sinan Kaya wrote:
>> Hi Vinod,
>>
>>>
>>
>> Can I have your ACK on your series if you are OK?
>
> Why ACK, shouldn't this be merged thru dmaengine tree? I would need ack
gt;> > memcpy interface. HW and driver doesn't support slave interface.
>> >
> Looks fine now.
>
> Reviewed-by: Andy Shevchenko <andy.shevche...@gmail.com>
>
Thanks. I'll wait until the end of the week to address your other comments.
I'm hoping to hear from devicetree
On 12/19/2015 1:37 PM, Andy Shevchenko wrote:
> On Thu, Dec 17, 2015 at 7:01 PM, Sinan Kaya <ok...@codeaurora.org> wrote:
>> In order to create a relationship model between the channels and the
>> management object, we are adding support for object hierarchy to the
&
On 11/25/2015 4:42 PM, Andy Gross wrote:
> On Sun, Nov 22, 2015 at 09:28:23PM -0500, Sinan Kaya wrote:
>> Creating a QCOM directory for all QCOM DMA source files.
>>
>> Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
>> ---
>
> Kind of nice having a diff
On 11/30/2015 3:59 AM, Vinod Koul wrote:
> On Sun, Nov 22, 2015 at 09:28:25PM -0500, Sinan Kaya wrote:
>> This patch adds support for hidma engine. The driver consists
>> of two logical blocks. The DMA engine interface and the
>> low-level interface. The hardware only s
On 11/30/2015 3:21 AM, Vinod Koul wrote:
> On Sun, Nov 22, 2015 at 09:28:24PM -0500, Sinan Kaya wrote:
>
>> +++ b/Documentation/ABI/testing/sysfs-platform-hidma-mgmt
>> @@ -0,0 +1,97 @@
>> +What: /sys/devices/platform/hidma-mgmt*/chan*/priority
>> +
I/.
>
> Arnd
>
I'm working on the sysfs documentation now.
Is there any other question regarding the patch series?
If not, I'd like to have a reviewed-by after the next post if acceptable.
--
Sinan Kaya
Qualcomm Technologies, Inc. on behalf of Qualcomm Innovation Center, Inc.
Qualcomm
w, the good stuff. Can you clarify your comment? I didn't understand it.
>
> I meant that DMAEngine uses
> /sys/class/dma
> dmaYchannelX/
> attr1
> attr2
> …
>
> layout.
>
I have posted v7 with this change.
--
Sinan Kaya
Qualcomm Technologies, Inc. on behalf of
parenthesis in assignments
* create subdirectories for channels in sysfs
Changes from V6: (https://lkml.org/lkml/2015/11/22/113)
* remove extra parenthesis
Sinan Kaya (3):
dma: qcom_bam_dma: move to qcom directory
dma: add Qualcomm Technologies HIDMA management driver
dma: add Qualcomm
This patch adds support for hidma engine. The driver consists
of two logical blocks. The DMA engine interface and the
low-level interface. The hardware only supports memcpy/memset
and this driver only support memcpy interface. HW and driver
doesn't support slave interface.
Signed-off-by: Sinan
driver is executed in hypervisor context and
is the main management entity for all channels provided by
the device.
Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
---
.../ABI/testing/sysfs-platform-hidma-mgmt | 97 +++
.../devicetree/bindings/dma/qcom_hidma_mgmt.txt
Creating a QCOM directory for all QCOM DMA source files.
Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
---
drivers/dma/Kconfig| 11 ++-
drivers/dma/Makefile | 2 +-
drivers/dma/qcom/Kconfig
sysfs ABI documentation
Changes from V5: (https://lkml.org/lkml/2015/11/15/137)
* Remove pm lock in ISR as it is redundant caught in lockdep.
* sparse warning for missing _iomem.
* sparse warning for static required.
Sinan Kaya (3):
dma: qcom_bam_dma: move to qcom directory
dma: add Qualcomm
Creating a QCOM directory for all QCOM DMA source files.
Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
---
drivers/dma/Kconfig| 11 ++-
drivers/dma/Makefile | 2 +-
drivers/dma/qcom/Kconfig
This patch adds support for hidma engine. The driver consists
of two logical blocks. The DMA engine interface and the
low-level interface. The hardware only supports memcpy/memset
and this driver only support memcpy interface. HW and driver
doesn't support slave interface.
Signed-off-by: Sinan
driver is executed in hypervisor context and
is the main management entity for all channels provided by
the device.
Signed-off-by: Sinan Kaya <ok...@codeaurora.org>
v6
* forgot to remove duplicate rc assignment.
* add missing _iomem from sparse warning.
---
.../ABI/testing
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