Re: [PATCH v3 2/5] bcache: implement PI controller for writeback rate

2017-10-07 Thread Coly Li
On 2017/10/8 下午12:57, Michael Lyle wrote: > Coly-- > > > On 10/07/2017 09:22 PM, Coly Li wrote: > [snip] >> rate:    488.2M/sec >> dirty:    91.7G >> target:    152.3G >> proportional:    -1.5G >> integral:    10.9G >> change:    0.0k/sec >> next io:    0ms > [snip] > >> The

Re: [PATCH v3 2/5] bcache: implement PI controller for writeback rate

2017-10-07 Thread Michael Lyle
Coly-- On 10/07/2017 09:22 PM, Coly Li wrote: [snip] rate: 488.2M/sec dirty: 91.7G target: 152.3G proportional: -1.5G integral: 10.9G change: 0.0k/sec next io:0ms [snip] The backing cached device size is 7.2TB, cache device is 1.4TB, block

Re: [PATCH v3 2/5] bcache: implement PI controller for writeback rate

2017-10-07 Thread Coly Li
On 2017/9/28 上午1:41, Michael Lyle wrote: > bcache uses a control system to attempt to keep the amount of dirty data > in cache at a user-configured level, while not responding excessively to > transients and variations in write rate. Previously, the system was a > PD controller; but the output