>> There is a use cases when architecture is 64-bit but hardware supports
>> only DMA to lower 4G of address space. E.g. NVMe device on RCar PCIe host.
>>
>> For such cases, it looks proper to call blk_queue_bounce_limit() with
>> mask set to 0x - thus making block layer to use bounce buff
Hi,
On Tue, Jan 10, 2017 at 4:48 AM, Nikita Yushchenko
wrote:
> Hi
>
> There is a use cases when architecture is 64-bit but hardware supports
> only DMA to lower 4G of address space. E.g. NVMe device on RCar PCIe host.
>
> For such cases, it looks proper to call blk_queue_bounce_limit() with
> ma
On Mon, Jan 09, 2017 at 11:48:11PM +0300, Nikita Yushchenko wrote:
> Hi
>
> There is a use cases when architecture is 64-bit but hardware supports
> only DMA to lower 4G of address space. E.g. NVMe device on RCar PCIe host.
The solution is to shoot the SOC designer. If that doesn't work use
swio
Hi
There is a use cases when architecture is 64-bit but hardware supports
only DMA to lower 4G of address space. E.g. NVMe device on RCar PCIe host.
For such cases, it looks proper to call blk_queue_bounce_limit() with
mask set to 0x - thus making block layer to use bounce buffers
for any
